Datasheet Texas Instruments ADS58H43
| Manufacturer | Texas Instruments |
| Series | ADS58H43 |
Quad-Channel, 14-Bit, 250-MSPS Receiver and Feedback IC
Datasheets
Quad-Channel, 250-MSPS Receiver and Feedback ADC datasheet
PDF, 2.3 Mb, File published: Nov 27, 2012
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Prices
Status
| ADS58H43IZCR | ADS58H43IZCRR | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No |
Packaging
| ADS58H43IZCR | ADS58H43IZCRR | |
|---|---|---|
| N | 1 | 2 |
| Pin | 144 | 144 |
| Package Type | ZCR | ZCR |
| Industry STD Term | NFBGA | NFBGA |
| JEDEC Code | S-PBGA-N | S-PBGA-N |
| Package QTY | 168 | 1000 |
| Carrier | JEDEC TRAY (10+1) | LARGE T&R |
| Device Marking | ADS58H43I | ADS58H43I |
| Width (mm) | 10 | 10 |
| Length (mm) | 10 | 10 |
| Thickness (mm) | .95 | .95 |
| Pitch (mm) | .8 | .8 |
| Max Height (mm) | 1.5 | 1.5 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | ADS58H43IZCR | ADS58H43IZCRR |
|---|---|---|
| # Input Channels | 4 | 4 |
| Analog Input BW, MHz | 500 | 500 |
| Analog Voltage AVDD(Max), V | 3.45 | 3.45 |
| Analog Voltage AVDD(Min), V | 1.8 | 1.8 |
| Interface | DDR LVDS | DDR LVDS |
| Logic Voltage DV/DD(Max), V | 2.0 | 2.0 |
| Logic Voltage DV/DD(Min), V | 1.7 | 1.7 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | NFBGA | NFBGA |
| Package Size: mm2:W x L, PKG | 144NFBGA: 100 mm2: 10 x 10(NFBGA) | 144NFBGA: 100 mm2: 10 x 10(NFBGA) |
| Power Consumption(Typ), mW | 1460 | 1460 |
| Resolution, Bits | 14 | 14 |
| SFDR, dB | 85 | 85 |
| SFDR(Typ), dB | 85 | 85 |
| SNR, dB | 70.5 | 70.5 |
| SNR(Typ), dB | 70.5 | 70.5 |
| Sample Rate(Max), MSPS | 250 | 250 |
| Special Features | Decimating Filter,Differential Inputs,Nap Mode,Out of Range Indicator,Power Down | Decimating Filter,Differential Inputs,Nap Mode,Out of Range Indicator,Power Down |
Eco Plan
| ADS58H43IZCR | ADS58H43IZCRR | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- Using Windowing With SNRBoost 3G TechnologyPDF, 498 Kb, File published: Aug 30, 2010
Coherency is a well-known requirement when using FFT techniques to examine the spectrum of the output of an analog-to-digital converter. SNRBoost(3G) technology results in loss in coherency, and this can be seen as an unstable noise floor in the spectrum. Windowing of the ADC output is a well-known solution to restore coherency and stable spectrum.However, windowing also modifies the amplitude o - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
Model Line
Series: ADS58H43 (2)
Manufacturer's Classification
- Semiconductors> RF & Microwave> Wideband Receivers
