Datasheet Texas Instruments ADS8323
| Manufacturer | Texas Instruments |
| Series | ADS8323 |
Pseudo Bipolar, 16-Bit, 500kSPS CMOS Analog-to-Digital Converter
Datasheets
ADS8323: 16-Bit, 500kSPS, microPower Sampling Analog-to-Digital Converter datasheet
PDF, 1.0 Mb, Revision: C, File published: Jan 5, 2010
Extract from the document
Prices
Status
| ADS8323Y/250 | ADS8323Y/250G4 | ADS8323Y/2K | ADS8323YB/250 | ADS8323YB/250G4 | |
|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No | No |
Packaging
| ADS8323Y/250 | ADS8323Y/250G4 | ADS8323Y/2K | ADS8323YB/250 | ADS8323YB/250G4 | |
|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 |
| Pin | 32 | 32 | 32 | 32 | 32 |
| Package Type | PBS | PBS | PBS | PBS | PBS |
| Industry STD Term | TQFP | TQFP | TQFP | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 250 | 250 | 2000 | 250 | 250 |
| Carrier | SMALL T&R | SMALL T&R | LARGE T&R | SMALL T&R | SMALL T&R |
| Device Marking | A23Y | A23Y | A23Y | B | A23Y |
| Width (mm) | 5 | 5 | 5 | 5 | 5 |
| Length (mm) | 5 | 5 | 5 | 5 | 5 |
| Thickness (mm) | 1 | 1 | 1 | 1 | 1 |
| Pitch (mm) | .5 | .5 | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download | Download |
Parametrics
| Parameters / Models | ADS8323Y/250 | ADS8323Y/250G4 | ADS8323Y/2K | ADS8323YB/250 | ADS8323YB/250G4 |
|---|---|---|---|---|---|
| # Input Channels | 1 | 1 | 1 | 1 | 1 |
| Analog Voltage AVDD(Max), V | 5.25 | 5.25 | 5.25 | 5.25 | 5.25 |
| Analog Voltage AVDD(Min), V | 4.75 | 4.75 | 4.75 | 4.75 | 4.75 |
| Architecture | SAR | SAR | SAR | SAR | SAR |
| Digital Supply(Max), V | 5.25 | 5.25 | 5.25 | 5.25 | 5.25 |
| Digital Supply(Min), V | 4.75 | 4.75 | 4.75 | 4.75 | 4.75 |
| INL(Max), +/-LSB | 4 | 4 | 4 | 4 | 4 |
| Input Range(Max), V | 5.25 | 5.25 | 5.25 | 5.25 | 5.25 |
| Input Type | Differential | Differential | Differential | Differential | Differential |
| Integrated Features | N/A | N/A | N/A | N/A | N/A |
| Interface | Parallel | Parallel | Parallel | Parallel | Parallel |
| Multi-Channel Configuration | N/A | N/A | N/A | N/A | N/A |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Package Group | TQFP | TQFP | TQFP | TQFP | TQFP |
| Package Size: mm2:W x L, PKG | 32TQFP: 49 mm2: 7 x 7(TQFP) | 32TQFP: 49 mm2: 7 x 7(TQFP) | 32TQFP: 49 mm2: 7 x 7(TQFP) | 32TQFP: 49 mm2: 7 x 7(TQFP) | 32TQFP: 49 mm2: 7 x 7(TQFP) |
| Power Consumption(Typ), mW | 85 | 85 | 85 | 85 | 85 |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
| Reference Mode | Ext,Int | Ext,Int | Ext,Int | Ext,Int | Ext,Int |
| Resolution, Bits | 16 | 16 | 16 | 16 | 16 |
| SINAD, dB | 83 | 83 | 83 | 83 | 83 |
| SNR, dB | 83 | 83 | 83 | 83 | 83 |
| Sample Rate (max), SPS | 500kSPS | 500kSPS | 500kSPS | 500kSPS | 500kSPS |
| Sample Rate(Max), MSPS | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 |
| THD(Typ), dB | -93 | -93 | -93 | -93 | -93 |
Eco Plan
| ADS8323Y/250 | ADS8323Y/250G4 | ADS8323Y/2K | ADS8323YB/250 | ADS8323YB/250G4 | |
|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant |
Application Notes
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
- Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
Model Line
Series: ADS8323 (5)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)
