Datasheet Texas Instruments AM3871CCYE80

Sitara Processor: ARM Cortex-A8, Ethernet 684-FCBGA 0 to 90

Datasheets

PDF, 2.5 Mb, Revision: D, File published: Jan 5, 2016

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

ARM CPU	1 ARM Cortex-A8
ARM MHz	1000 Max.
Applications	Communications Equipment,Enterprise Systems,Industrial,Personal Electronics
CAN	2
DRAM	LPDDR,DDR2,DDR3
Display Options	HDVPSS
EMAC	10/100/1000
Graphics Acceleration	N/A
I2C	4
On-Chip L2 Cache	512 KB (ARM Cortex-A8)
Operating Systems	Linux,Windows Embedded CE
Operating Temperature Range	0 to 90 C
Other On-Chip Memory	128 KB
Rating	Catalog
SPI	4
UART	6 SCI
USB	2
Video Port	N/A Configurable

RoHS

Compliant

Evaluation Modules & Boards: TMDXEVM8148
DM814x /AM387x Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)

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TMS320DM814x/AM387x Power Estimation Spreadsheet (Rev. A)
PDF, 18 Kb, Revision: A, File published: Sep 10, 2012
This article describes how to model power consumption for a user's application and to present some measured power scenarios for the TMS320DM814x DaVinciв„ў digital media processors and AM387x Sitaraв„ў ARMВ® microprocessors (MPUs) PG2.x and PG3.x samples using a provided power estimation spreadsheet.This article has been contributed to the TI Developer Wiki. To see the most recen
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Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB
PDF, 97 Kb, File published: Nov 25, 2009
This application note contains instructions for implementing Canny Edge Detection algorithm using VLIB. The general ideas given here can also be applied for an application which calls a sequence of VLIB functions in a block-based manner.
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High-Speed Interface Layout Guidelines (Rev. G)
PDF, 814 Kb, Revision: G, File published: Jul 27, 2017
As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.

Series: AM3871 (2)