Datasheet Texas Instruments AM5K2E02

Manufacturer	Texas Instruments
Series	AM5K2E02

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Parametrics

Parameters / Models	AM5K2E02ABD25	AM5K2E02ABD4	AM5K2E02ABDA25	AM5K2E02ABDA4	AM5K2E02XABD25
ARM CPU	2 ARM Cortex-A15	2 ARM Cortex-A15	2 ARM Cortex-A15	2 ARM Cortex-A15	2 ARM Cortex-A15
ARM MHz, Max.	1250,1400	1250,1400	1250,1400	1250,1400	1250,1400
Applications	Industrial	Industrial	Industrial	Industrial	Industrial
DRAM	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L
EMAC	8-Port 1Gb Switch	8-Port 1Gb Switch	8-Port 1Gb Switch	8-Port 1Gb Switch	8-Port 1Gb Switch
I2C	3	3	3	3	3
On-Chip L2 Cache	4096 KB (ARM Cluster)	4096 KB (ARM Cluster)	4096 KB (ARM Cluster)	4096 KB (ARM Cluster)	4096 KB (ARM Cluster)
Operating Systems	SYS/BIOS,Linux,VxWorks,Integrity	SYS/BIOS,Linux,VxWorks,Integrity	SYS/BIOS,Linux,VxWorks,Integrity	SYS/BIOS,Linux,VxWorks,Integrity	SYS/BIOS,Linux,VxWorks,Integrity
Operating Temperature Range, C	0 to 85,-40 to 100	0 to 85,-40 to 100	0 to 85,-40 to 100	0 to 85,-40 to 100	0 to 85,-40 to 100
Other On-Chip Memory	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB
PCI/PCIe	4 PCIe Gen2	4 PCIe Gen2	4 PCIe Gen2	4 PCIe Gen2	4 PCIe Gen2
Rating	Catalog	Catalog	Catalog	Catalog	Catalog
SPI	3	3	3	3	3
Serial I/O	Hyperlink,I2C,SPI,TSIP,UART,USB	Hyperlink,I2C,SPI,TSIP,UART,USB	Hyperlink,I2C,SPI,TSIP,UART,USB	Hyperlink,I2C,SPI,TSIP,UART,USB	Hyperlink,I2C,SPI,TSIP,UART,USB
UART, SCI	2	2	2	2	2
USB	2	2	2	2	2

Eco Plan

Application Notes

• Download
  Clocking Spreadsheet for K2E Device Family
  PDF, 22 Kb, File published: Jan 26, 2017
  This document discusses the internal clocking architecture of Texas Instruments K2Ex Digital Signal Processors (DSP) using a provided clocking spreadsheet.The 66AK2Ex and AM5K2Ex devices have similar internal clocking architecture and peripherals except the corepac. The 66AK2Ex devices have both DSP corepac and ARM corepac, whereas, the AM5K2Ex devices have ARM corepac only.Use the K
• Download
  Keystone II DDR3 Initialization
  PDF, 73 Kb, File published: Jan 26, 2015
  This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
• Download
  Throughput Performance Guide for KeyStone II Devices (Rev. B)
  PDF, 866 Kb, Revision: B, File published: Dec 22, 2015
  This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
• Download
  Keystone II DDR3 Debug Guide
  PDF, 143 Kb, File published: Oct 16, 2015
  This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
• Download
  Power Management of KS2 Device (Rev. C)
  PDF, 61 Kb, Revision: C, File published: Jul 15, 2016
  This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
• Download
  Hardware Design Guide for KeyStone II Devices
  PDF, 1.8 Mb, File published: Mar 24, 2014
• Download
  PCIe Use Cases for KeyStone Devices
  PDF, 320 Kb, File published: Dec 13, 2011
• Download
  Clocking Design Guide for KeyStone Devices
  PDF, 1.5 Mb, File published: Nov 9, 2010
• Download
  Optimizing Loops on the C66x DSP
  PDF, 585 Kb, File published: Nov 9, 2010
• Download
  The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
  PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
  The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
• Download
  DDR3 Design Requirements for KeyStone Devices (Rev. B)
  PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
• Download
  Multicore Programming Guide (Rev. B)
  PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
  As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
• Download
  Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
  PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
  This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

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Manufacturer's Classification

• Semiconductors> Processors> Sitara Processors> ARM Cortex-A15> AM5K2Ex