Datasheet Texas Instruments AM5K2E04XABD25
| Manufacturer | Texas Instruments |
| Series | AM5K2E04 |
| Part Number | AM5K2E04XABD25 |
Sitara Processor: Quad ARM Cortex-A15 1089-FCBGA 0 to 85
Datasheets
AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet
PDF, 1.8 Mb, Revision: D, File published: Mar 11, 2015
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 1089 | 1089 |
| Package Type | ABD | ABD |
| Package QTY | 40 | 40 |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
| Device Marking | AM5K2E04XABD | @2012 TI |
| Width (mm) | 27 | 27 |
| Length (mm) | 27 | 27 |
| Thickness (mm) | 2.98 | 2.98 |
| Mechanical Data | Download | Download |
Parametrics
| ARM CPU | 4 ARM Cortex-A15 |
| ARM MHz | 1250,1400 Max. |
| Applications | Industrial |
| DRAM | DDR3,DDR3L |
| EMAC | 8-Port 1Gb Switch |
| I2C | 3 |
| On-Chip L2 Cache | 4096 KB (ARM Cluster) |
| Operating Systems | SYS/BIOS,Linux,VxWorks,Integrity |
| Operating Temperature Range | -40 to 100,0 to 85 C |
| Other On-Chip Memory | 2048 KB |
| PCI/PCIe | 4 PCIe Gen2 |
| Rating | Catalog |
| SPI | 3 |
| Serial I/O | Hyperlink,I2C,SPI,TSIP,UART,USB |
| UART | 2 SCI |
| USB | 2 |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: XEVMK2EX
K2E Development Board
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: EVMK2EX
K2E Development Board
Lifecycle Status: Preview (Device has been announced but is not in production. Samples may or may not be available)
Application Notes
- Power Consumption Summary for K2E System-on-Chip (SoC) Device FamilyPDF, 65 Kb, File published: Jun 14, 2017
This application report discusses estimating the power consumption of Texas Instruments' K2Ex Digital Signal Processors (DSP) using a provided device-specific power spreadsheet. It should be noted that the power model is applicable for all silicon revisions. - Clocking Spreadsheet for K2E Device FamilyPDF, 22 Kb, File published: Jan 26, 2017
This document discusses the internal clocking architecture of Texas Instruments K2Ex Digital Signal Processors (DSP) using a provided clocking spreadsheet.The 66AK2Ex and AM5K2Ex devices have similar internal clocking architecture and peripherals except the corepac. The 66AK2Ex devices have both DSP corepac and ARM corepac, whereas, the AM5K2Ex devices have ARM corepac only.Use the K - Keystone II DDR3 InitializationPDF, 73 Kb, File published: Jan 26, 2015
This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller. - Throughput Performance Guide for KeyStone II Devices (Rev. B)PDF, 866 Kb, Revision: B, File published: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access. - Keystone II DDR3 Debug GuidePDF, 143 Kb, File published: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device. - Power Management of KS2 Device (Rev. C)PDF, 61 Kb, Revision: C, File published: Jul 15, 2016
This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices. - Hardware Design Guide for KeyStone II DevicesPDF, 1.8 Mb, File published: Mar 24, 2014
- PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, File published: Dec 13, 2011
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, File published: Nov 9, 2010
- Optimizing Loops on the C66x DSPPDF, 585 Kb, File published: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
Model Line
Series: AM5K2E04 (4)
- AM5K2E04XABD25 AM5K2E04XABD4 AM5K2E04XABDA25 AM5K2E04XABDA4
Manufacturer's Classification
- Semiconductors > Processors > Sitara Processors > ARM Cortex-A15 > AM5K2Ex
