Datasheet Texas Instruments CD54AC112

ManufacturerTexas Instruments
SeriesCD54AC112
Datasheet Texas Instruments CD54AC112

Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset

Datasheets

CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, File published: Jan 17, 2003
Extract from the document

Prices

Status

CD54AC112F3A
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

CD54AC112F3A
N1
Pin16
Package TypeJ
Industry STD TermCDIP
JEDEC CodeR-GDIP-T
Package QTY1
CarrierTUBE
Device MarkingCD54AC112F3A
Width (mm)6.92
Length (mm)19.56
Thickness (mm)4.57
Pitch (mm)2.54
Max Height (mm)5.08
Mechanical DataDownload

Eco Plan

CD54AC112F3A
RoHSSee ti.com

Application Notes

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, File published: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Model Line

Series: CD54AC112 (1)

Manufacturer's Classification

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers