Datasheet Texas Instruments CD74HC73
Manufacturer | Texas Instruments |
Series | CD74HC73 |
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Datasheets
CD54HC73, CD74HC73, CD74HCT73 datasheet
PDF, 724 Kb, Revision: E, File published: Aug 21, 2003
Extract from the document
Prices
Status
CD74HC73E | CD74HC73EE4 | CD74HC73M | CD74HC73M96 | CD74HC73M96G4 | CD74HC73MG4 | CD74HC73MT | |
---|---|---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No | No | No | No | No | Yes |
Packaging
CD74HC73E | CD74HC73EE4 | CD74HC73M | CD74HC73M96 | CD74HC73M96G4 | CD74HC73MG4 | CD74HC73MT | |
---|---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
Pin | 14 | 14 | 14 | 14 | 14 | 14 | 14 |
Package Type | N | N | D | D | D | D | D |
Industry STD Term | PDIP | PDIP | SOIC | SOIC | SOIC | SOIC | SOIC |
JEDEC Code | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 25 | 25 | 50 | 2500 | 2500 | 50 | 250 |
Carrier | TUBE | TUBE | TUBE | LARGE T&R | LARGE T&R | TUBE | SMALL T&R |
Device Marking | CD74HC73E | CD74HC73E | HC73M | HC73M | HC73M | HC73M | HC73M |
Width (mm) | 6.35 | 6.35 | 3.91 | 3.91 | 3.91 | 3.91 | 3.91 |
Length (mm) | 19.3 | 19.3 | 8.65 | 8.65 | 8.65 | 8.65 | 8.65 |
Thickness (mm) | 3.9 | 3.9 | 1.58 | 1.58 | 1.58 | 1.58 | 1.58 |
Pitch (mm) | 2.54 | 2.54 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 |
Max Height (mm) | 5.08 | 5.08 | 1.75 | 1.75 | 1.75 | 1.75 | 1.75 |
Mechanical Data | Download | Download | Download | Download | Download | Download | Download |
Parametrics
Parameters / Models | CD74HC73E | CD74HC73EE4 | CD74HC73M | CD74HC73M96 | CD74HC73M96G4 | CD74HC73MG4 | CD74HC73MT |
---|---|---|---|---|---|---|---|
Bits | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
F @ Nom Voltage(Max), Mhz | 70 | 70 | 70 | 70 | 70 | 70 | 70 |
ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 |
Output Drive (IOL/IOH)(Max), mA | -6/6 | -6/6 | -6/6 | -6/6 | -6/6 | -6/6 | -6/6 |
Package Group | PDIP | PDIP | SOIC | SOIC | SOIC | SOIC | SOIC |
Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) |
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No | No | No | No |
Technology Family | HC | HC | HC | HC | HC | HC | HC |
VCC(Max), V | 6 | 6 | 6 | 6 | 6 | 6 | 6 |
VCC(Min), V | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
Voltage(Nom), V | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 |
tpd @ Nom Voltage(Max), ns | 40 | 40 | 40 | 40 | 40 | 40 | 40 |
Eco Plan
CD74HC73E | CD74HC73EE4 | CD74HC73M | CD74HC73M96 | CD74HC73M96G4 | CD74HC73MG4 | CD74HC73MT | |
---|---|---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Pb Free | Yes | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
Model Line
Series: CD74HC73 (7)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop