Datasheet Texas Instruments CD74HCT75
| Manufacturer | Texas Instruments |
| Series | CD74HCT75 |
High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch
Datasheets
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 datasheet
PDF, 694 Kb, Revision: F, File published: Oct 13, 2003
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Status
| CD74HCT75E | CD74HCT75EE4 | CD74HCT75M | CD74HCT75MG4 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No |
Packaging
| CD74HCT75E | CD74HCT75EE4 | CD74HCT75M | CD74HCT75MG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 16 | 16 | 16 | 16 |
| Package Type | N | N | D | D |
| Industry STD Term | PDIP | PDIP | SOIC | SOIC |
| JEDEC Code | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G |
| Package QTY | 25 | 25 | 40 | 40 |
| Carrier | TUBE | TUBE | TUBE | TUBE |
| Device Marking | CD74HCT75E | CD74HCT75E | HCT75M | HCT75M |
| Width (mm) | 6.35 | 6.35 | 3.91 | 3.91 |
| Length (mm) | 19.3 | 19.3 | 9.9 | 9.9 |
| Thickness (mm) | 3.9 | 3.9 | 1.58 | 1.58 |
| Pitch (mm) | 2.54 | 2.54 | 1.27 | 1.27 |
| Max Height (mm) | 5.08 | 5.08 | 1.75 | 1.75 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | CD74HCT75E | CD74HCT75EE4 | CD74HCT75M | CD74HCT75MG4 |
|---|---|---|---|---|
| 3-State Output | No | No | No | No |
| Bits | 4 | 4 | 4 | 4 |
| F @ Nom Voltage(Max), Mhz | 25 | 25 | 25 | 25 |
| ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 |
| Operating Temperature Range, C | -55 to 125 | -55 to 125 | -55 to 125 | -55 to 125 |
| Output Drive (IOL/IOH)(Max), mA | 4/-4 | 4/-4 | 4/-4 | 4/-4 |
| Package Group | PDIP | PDIP | SOIC | SOIC |
| Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No |
| Technology Family | HCT | HCT | HCT | HCT |
| VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 |
| VCC(Min), V | 4.5 | 4.5 | 4.5 | 4.5 |
| Voltage(Nom), V | 5 | 5 | 5 | 5 |
| tpd @ Nom Voltage(Max), ns | 35 | 35 | 35 | 35 |
Eco Plan
| CD74HCT75E | CD74HCT75EE4 | CD74HCT75M | CD74HCT75MG4 | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
| Pb Free | Yes | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
Model Line
Series: CD74HCT75 (4)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> Other Latch
