Datasheet Texas Instruments CDC208DW
| Manufacturer | Texas Instruments |
| Series | CDC208 |
| Part Number | CDC208DW |
5V Dual 1-to-4 clock driver 20-SOIC
Datasheets
Dual 1-Line To 4-Line Clock Drivers With 3-State Outputs datasheet
PDF, 1.1 Mb, Revision: F, File published: Oct 28, 1998
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 20 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | CDC208 |
| Width (mm) | 7.5 |
| Length (mm) | 12.8 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | Download |
Parametrics
| Input Frequency(Max) | 60 MHz |
| Input Level | TTL |
| Number of Outputs | 8 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 60 MHz |
| Output Level | CMOS |
| Package Group | SOIC |
| Package Size: mm2:W x L | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG |
| Rating | Catalog |
| VCC Out | 5 V |
Eco Plan
| RoHS | Compliant |
Application Notes
- Minimizing Clock Driver Output Skew Using Ganged OutputsPDF, 53 Kb, File published: Jan 1, 1994
This document helps designers use existing clock-driver products to drive large loads while maintaining a minimum amount of skew between the device outputs. The emphasis of this document is using parallel or ganged outputs to drive loads. A performance evaluation of the CDC201 is provided.
Model Line
Series: CDC208 (8)
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Single-Ended
