Datasheet Texas Instruments CDC2509APWRG4
| Manufacturer | Texas Instruments |
| Series | CDC2509A |
| Part Number | CDC2509APWRG4 |
3.3-V Phase-Lock Loop Clock Driver With 3-State Outputs 24-TSSOP 0 to 70
Datasheets
CDC2509A: 3.3 V Phase Lock Loop Clock Driver (Rev. C)
PDF, 614 Kb, Revision: C, File published: Dec 2, 2004
Prices
Status
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CK2509A |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Eco Plan
| RoHS | Compliant |
| Pb Free | Yes |
Application Notes
- Using CDC2509A/CDC2510A PLL With Spread Spectrum Clocking (SSC)PDF, 454 Kb, File published: Jan 5, 1999
This application note describes the CDC2509A/2510A [1] phase-lock loop clockdrivers and their use with spread spectrum clocking system. This application note gives SSC system performance measurements and parameter measurementinstructions. - High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, Revision: A, File published: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
Model Line
Series: CDC2509A (2)
- CDC2509APWR CDC2509APWRG4
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers
