Datasheet Texas Instruments CDC2582
| Manufacturer | Texas Instruments |
| Series | CDC2582 |
3.3V PLL Clock Driver with LVPECL Input and 12 LVTTL Outputs
Datasheets
3.3-V Phase-Lock Loop Clock Driver With Differential LVPECL Clock Inputs datasheet
PDF, 150 Kb, Revision: B, File published: Feb 1, 1996
Extract from the document
Prices
Status
| CDC2582PAH | CDC2582PAHG4 | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes |
Packaging
| CDC2582PAH | CDC2582PAHG4 | |
|---|---|---|
| N | 1 | 2 |
| Pin | 52 | 52 |
| Package Type | PAH | PAH |
| Industry STD Term | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 160 | 160 |
| Carrier | JEDEC TRAY (10+1) | JEDEC TRAY (10+1) |
| Device Marking | CDC2582 | CDC2582 |
| Width (mm) | 10 | 10 |
| Length (mm) | 10 | 10 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | CDC2582PAH | CDC2582PAHG4 |
|---|---|---|
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps | 200 | 200 |
| Number of Outputs | 12 | 12 |
| Operating Frequency Range(Max), MHz | 100 | 100 |
| Operating Frequency Range(Min), MHz | 25 | 25 |
| Package Group | TQFP | TQFP |
| Package Size: mm2:W x L, PKG | 52TQFP: 144 mm2: 12 x 12(TQFP) | 52TQFP: 144 mm2: 12 x 12(TQFP) |
| Rating | Catalog | Catalog |
| VCC, V | 3.3 | 3.3 |
| t(phase error), ps | 500 | 500 |
| tsk(o), ps | 500 | 500 |
Eco Plan
| CDC2582PAH | CDC2582PAHG4 | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- Phase-Lock Loop-Based (PLL) Clock Drivers: Benefits Versus Costs (Rev. A)PDF, 51 Kb, Revision: A, File published: Mar 1, 1997
This document provides an overview of a PLL clock driver. The advantages and disadvantages of PLLs and the cost in designs are discussed. TI manufactures three low-voltage high-performance PLL clock drivers, the CDC2582, CDC2586, and the CDC2586. - Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, File published: Apr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
Model Line
Series: CDC2582 (2)
Manufacturer's Classification
- Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers
