PDF, 131 Kb, Revision: B, File published: May 21, 1997
Extract from the document
CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MAY 1997 D
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D DW PACKAGE
(TOP VIEW) Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
TTL-Compatible Inputs and Outputs
Distributes One Clock Input to Eight
Outputs
Distributed VCC and Ground Pins Reduce
Switching Noise
High-Drive Outputs (– 48-mA IOH,
48-mA IOL)
State-of-the-Art EPIC-О™О™B пЈЄ BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline (DW) and Shrink VCC …
