Datasheet Texas Instruments CDC3S04YFFR

Quad Sine-Wave Clock Buffer with LDO 20-DSBGA -40 to 85

Datasheets

PDF, 1.5 Mb, Revision: C, File published: Jul 25, 2012

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Additive RMS Jitter(Typ)	300 fs
Input Frequency(Max)	52 MHz
Input Level	SINE
Number of Outputs	4
Operating Temperature Range	-40 to 85 C
Output Frequency(Max)	52 MHz
Output Level	SINE
Package Group	DSBGA
Package Size: mm2:W x L	See datasheet (DSBGA) PKG
Rating	Catalog
VCC Out	1.8 V

RoHS

Compliant

Evaluation Modules & Boards: CDC3S04EVM
CDC3S04EVM Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
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Using the CDC3S04
PDF, 110 Kb, File published: Apr 18, 2010
When designing a single-ended clock tree, a system designer can choose between two commonly-used waveform types: rectangular or sinusoidal. This application note gives a short overview of both signal types and shows the advantages and disadvantages of each using the CDC3S04 quad sine-wave clock buffer with an integrated low-dropout regulator (LDO). Additionally, the clipped sinusoidal waveform is
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Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04 (Rev. A)
PDF, 12.8 Mb, Revision: A, File published: Jun 21, 2010
This application report is an overview on how power supply noise affects some key specifications of the CDC3S04 sine wave buffer. The ripple in the power supply induces additional harmonics in the frequency spectrum and spurs in the phase noise plot, thus degrading the overall jitter and EMI performance. Decoupling capacitors significantly minimize these effects. This document provides guidelines

Series: CDC3S04 (1)