Datasheet Texas Instruments CDC3S04

Manufacturer	Texas Instruments
Series	CDC3S04

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Parametrics

Parameters / Models	CDC3S04YFFR
Additive RMS Jitter(Typ), fs	300
Input Frequency(Max), MHz	52
Input Level	SINE
Number of Outputs	4
Operating Temperature Range, C	-40 to 85
Output Frequency(Max), MHz	52
Output Level	SINE
Package Group	DSBGA
Package Size: mm2:W x L, PKG	See datasheet (DSBGA)
Rating	Catalog
VCC Out, V	1.8

Eco Plan

Application Notes

• Download
  Using the CDC3S04
  PDF, 110 Kb, File published: Apr 18, 2010
  When designing a single-ended clock tree, a system designer can choose between two commonly-used waveform types: rectangular or sinusoidal. This application note gives a short overview of both signal types and shows the advantages and disadvantages of each using the CDC3S04 quad sine-wave clock buffer with an integrated low-dropout regulator (LDO). Additionally, the clipped sinusoidal waveform is
• Download
  Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04 (Rev. A)
  PDF, 12.8 Mb, Revision: A, File published: Jun 21, 2010
  This application report is an overview on how power supply noise affects some key specifications of the CDC3S04 sine wave buffer. The ripple in the power supply induces additional harmonics in the frequency spectrum and spurs in the phase noise plot, thus degrading the overall jitter and EMI performance. Decoupling capacitors significantly minimize these effects. This document provides guidelines

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Manufacturer's Classification

• Semiconductors> Clock and Timing> Clock Buffers> Single-Ended