Datasheet Texas Instruments CDC706PWR

Custom Programmed 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP

Datasheets

PDF, 1.4 Mb, Revision: B, File published: Feb 11, 2008

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Lifecycle Status	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No

RoHS

Compliant

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CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)
PDF, 155 Kb, Revision: A, File published: Nov 28, 2007
This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs.
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High Speed Layout Guidelines (Rev. A)
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Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection
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Clock Recommendations for the DM643x EVM
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The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m

Series: CDC706 (4)