Datasheet Texas Instruments CDCF5801ADBQ

Low Jitter PLL Based Multiplier/Divider with programmable delay lines down to sub 10ps 24-SSOP -40 to 85

Datasheets

PDF, 603 Kb, File published: Mar 15, 2006

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Input Level	HSTL,LVPECL,LVTTL
Number of Outputs	1
Operating Temperature Range	-40 to 85 C
Output Frequency(Max)	280 MHz
Output Level	LVDS,LVPECL,LVTTL
Package Group	SSOP
Package Size: mm2:W x L	24SSOP: 52 mm2: 6 x 8.65(SSOP) PKG
Programmability	Pin configuration
Special Features	Spread Spectrum Clocking (SSC),3.3V Vcc/Vdd
VCC Core	3.3 V
VCC Out	3.3 V

RoHS

Compliant

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A General Guideline: How to Use the CDCF5801A for Phase Alignment/Adjustment (Rev. B)
PDF, 129 Kb, Revision: B, File published: Oct 21, 2005
Unlike regular PLLs, the CDCF5801 has an extra phase aligner. Using this extra phase aligner, the CDCF5801 can align two different clock phases, even with differentfrequencies. Examples of where phase alignment may be useful include:В· Applications where two clock buffers' outputs need to be alignedВ· Applications that require data synchronization with SERDESВ· Applications that require stati
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Using Configurable Active Delay Elements in CDCF5801A Feedback Loop
PDF, 43 Kb, File published: Sep 15, 2004
Using Configurable Active Delay Elements in CDCF5801 Feedback Loop

Series: CDCF5801A (4)