Datasheet Texas Instruments CDCLVD110VF

Manufacturer	Texas Instruments
Series	CDCLVD110
Part Number	CDCLVD110VF

1-to-10 LVDS clock buffer up to 900MHz with minimum skew for clock distribution 32-LQFP -40 to 85

Datasheets

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PDF, 513 Kb, Revision: C, File published: Jan 14, 2008

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CDCLVD110 www.ti.com SCAS684C вЂ“ SEPTEMBER 2002 вЂ“ REVISED JANUARY 2008 Not Recommended for New Designs
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
FEATURES 1 LQFP PACKAGE Low-Output Skew 2000 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS
VDD Supply voltage VIC Receiver common-mode input voltage TA Operating free-air temperature MIN NOM MAX UNIT 2.375 2.5 2.625 V 0.5|VID| VDD вЂ“ 0.5|VID| V вЂ“40 85 В°C ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 100в„¦ 250 450 600 mV 50 mV вЂ“40В°C to 85В°C 0.95 1.2 1.45 V 350 mV DRIVER
|VOD| Differential output voltage О”VOD VOD magnitude change VOS Offset voltage О”VOS VOS magnitude change IOS Output short circuit current VBB Reference output voltage VDD = 2.5 V, IBB = вЂ“100 ВµA CO Output capacitance VO = VDD or GND VO = 0 V вЂ“20 |VOD| = 0 V 20
1.15 1.25 1.35 3 Submit Documentation Feedback Copyright В© 2002вЂ“2008, Texas Instruments Incorporated Product Folder Link(s) :CDCLVD110 mA
V
pF 3 CDCLVD110 www.ti.com SCAS684C вЂ“ SEPTEMBER 2002 вЂ“ REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECEIVER
VIDH Input threshold high VIDL Input threshold low |VID| Input differential voltage IIH Input current, CLK0/CLK0, CLK1/CLK1 IIL
CI Input capacitance 100 mV вЂ“100 mV 200 mV VI = VDD вЂ“5 VI = 0 V ВµA 5 VI = VDD or GND 3 pF SUPPLY CURRENT
IDD Supply current IDDZ Full loaded All outputs enabled and loaded, RL = 100 в„¦, f = 0 Hz No load Outputs enabled, no output load, f = 0 Hz 35 3-State All outputs 3-state by control logic, f = 0 Hz 35 130
mA JITTER CHARACTERISTICS
characterized with CDCLVD110 performance EVM, VDD = 3.3 V, OUTPUTS NOT UNDER TEST are terminated to 50в„¦
PARAMETER
tjitterLVDS Additive phase jitter from input to
LVDS output Q3 and Q3 TEST CONDITIONS MIN TYP 12 kHz to 5 MHz, fout = 30.72 MHz 650 12 kHz to 20 MHz, fout = 125 MHz 299 MAX UNIT
fs rms LVDS вЂ” SWITCHING CHARACTERISTICS …

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Status

Lifecycle Status	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	32
Package Type	VF
Industry STD Term	LQFP
JEDEC Code	S-PQFP-G
Package QTY	250
Carrier	JEDEC TRAY (10+1)
Device Marking	CDCLVD110
Width (mm)	7
Length (mm)	7
Thickness (mm)	1.4
Pitch (mm)	.8
Max Height (mm)	1.6
Mechanical Data	Download

Eco Plan

RoHS

Compliant

Application Notes

Download
Benefits of Using TI's Non-PLL Clock Buffer: Best in Class Phase Noise/Phase
PDF, 560 Kb, File published: Jul 18, 2003
This application report presents various jitter and phase noise measurements of three differential clock drivers. A Texas Instruments device was compared to two independent competitor devices. This report proves that clock buffer selection does have an impact on the total system timing budget, particularly when the system has two different input signals connected. Buffers must be able to resist th
Download
DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
PDF, 135 Kb, File published: Feb 19, 2003
Download
AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
PDF, 417 Kb, Revision: C, File published: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Model Line

Series: CDCLVD110 (4)

CDCLVD110VF CDCLVD110VFG4 CDCLVD110VFR CDCLVD110VFRG4

Manufacturer's Classification

Semiconductors > Clock and Timing > Clock Buffers > Differential