Datasheet Texas Instruments CDCLVP110MVFR
| Manufacturer | Texas Instruments |
| Series | CDCLVP110 |
| Part Number | CDCLVP110MVFR |
1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
Datasheets
Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet
PDF, 653 Kb, Revision: D, File published: Jan 11, 2011
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 32 |
| Package Type | VF |
| Industry STD Term | LQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | CDCLVP110 |
| Width (mm) | 7 |
| Length (mm) | 7 |
| Thickness (mm) | 1.4 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.6 |
| Mechanical Data | Download |
Parametrics
| Additive RMS Jitter(Typ) | 300 fs |
| Input Frequency(Max) | 3500 MHz |
| Input Level | HSTL,LVPECL |
| Number of Outputs | 10 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 3500 MHz |
| Output Level | LVPECL |
| Package Group | LQFP |
| Package Size: mm2:W x L | 32LQFP: 81 mm2: 9 x 9(LQFP) PKG |
| Rating | Catalog |
| VCC | 2.5,3.3 V |
| VCC Out | 2.5,3.3 V |
Eco Plan
| RoHS | Compliant |
Application Notes
- Advantage of Using TI's Lowest Jitter Differential Clock BufferPDF, 221 Kb, File published: Aug 20, 2003
Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz - PCB Layout Guidelines for CDCLVP110PDF, 70 Kb, File published: Jun 12, 2002
This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature. - Clocking Design Guidelines: Unused PinsPDF, 158 Kb, File published: Nov 19, 2015
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, File published: Feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revision: C, File published: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Model Line
Series: CDCLVP110 (6)
- CDCLVP110MVFR CDCLVP110MVFRG4 CDCLVP110VF CDCLVP110VFG4 CDCLVP110VFR CDCLVP110VFRG4
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Differential
