Datasheet Texas Instruments CDCLVP110MVFRG4

1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85

Datasheets

PDF, 653 Kb, Revision: D, File published: Jan 11, 2011

Extract from the document

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Additive RMS Jitter(Typ)	300 fs
Input Frequency(Max)	3500 MHz
Input Level	HSTL,LVPECL
Number of Outputs	10
Operating Temperature Range	-40 to 85 C
Output Frequency(Max)	3500 MHz
Output Level	LVPECL
Package Group	LQFP
Package Size: mm2:W x L	32LQFP: 81 mm2: 9 x 9(LQFP) PKG
Rating	Catalog
VCC	2.5,3.3 V
VCC Out	2.5,3.3 V

RoHS

Compliant

Download
Advantage of Using TI's Lowest Jitter Differential Clock Buffer
PDF, 221 Kb, File published: Aug 20, 2003
Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz
Download
PCB Layout Guidelines for CDCLVP110
PDF, 70 Kb, File published: Jun 12, 2002
This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature.
Download
Clocking Design Guidelines: Unused Pins
PDF, 158 Kb, File published: Nov 19, 2015
Download
DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
PDF, 135 Kb, File published: Feb 19, 2003
Download
AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
PDF, 417 Kb, Revision: C, File published: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Series: CDCLVP110 (6)