Datasheet Texas Instruments CDCLVP1212RHAT
Manufacturer | Texas Instruments |
Series | CDCLVP1212 |
Part Number | CDCLVP1212RHAT |
Low Jitter, 2-Input Selectable 1:12 Universal-to-LVPECL Buffer 40-VQFN
Datasheets
CDCLVP1212 LVPECL Output, High-Performance Clock Buffer datasheet
PDF, 1.1 Mb, Revision: E, File published: Dec 2, 2015
Extract from the document
Prices
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | Yes |
Packaging
Pin | 40 | 40 |
Package Type | RHA | RHA |
Industry STD Term | VQFN | VQFN |
JEDEC Code | S-PQFP-N | S-PQFP-N |
Package QTY | 250 | 250 |
Carrier | SMALL T&R | SMALL T&R |
Device Marking | 1212 | CDCLVP |
Width (mm) | 6 | 6 |
Length (mm) | 6 | 6 |
Thickness (mm) | .9 | .9 |
Pitch (mm) | .5 | .5 |
Max Height (mm) | 1 | 1 |
Mechanical Data | Download | Download |
Parametrics
Additive RMS Jitter(Typ) | 57 fs |
Input Frequency(Max) | 2000 MHz |
Input Level | LVCMOS,LVDS,LVPECL |
Number of Outputs | 12 |
Output Frequency(Max) | 2000 MHz |
Output Level | LVPECL |
Package Group | VQFN |
Package Size: mm2:W x L | 40VQFN: 36 mm2: 6 x 6(VQFN) PKG |
Rating | Catalog |
VCC | 2.5,3.3 V |
VCC Out | 2.5,3.3 V |
Eco Plan
RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: CDCLVP1212EVM
CDCLVP1212 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Clocking Design Guidelines: Unused PinsPDF, 158 Kb, File published: Nov 19, 2015
Model Line
Series: CDCLVP1212 (2)
- CDCLVP1212RHAR CDCLVP1212RHAT
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Differential