Datasheet Texas Instruments CDCP1803RGER
| Manufacturer | Texas Instruments |
| Series | CDCP1803 |
| Part Number | CDCP1803RGER |
1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85
Datasheets
1:3 LVPECL Clock Buffer with Programmable Divider, CDCP1803 datasheet
PDF, 873 Kb, Revision: F, File published: Dec 4, 2013
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 24 | 24 |
| Package Type | RGE | RGE |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 3000 | 3000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | 1803 | CDCP |
| Width (mm) | 4 | 4 |
| Length (mm) | 4 | 4 |
| Thickness (mm) | .88 | .88 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | Download | Download |
Parametrics
| Additive RMS Jitter(Typ) | 150 fs |
| Input Frequency(Max) | 800 MHz |
| Input Level | LVPECL |
| Number of Outputs | 3 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 800 MHz |
| Output Level | LVPECL |
| Package Group | VQFN |
| Package Size: mm2:W x L | 24VQFN: 16 mm2: 4 x 4(VQFN) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| VCC Out | 3.3 V |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: ADS6122EVM
ADS6122 12-Bit, 65-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS6143EVM
ADS6143 14-Bit, 80-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS6123EVM
ADS6123 12-Bit, 80-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS6124EVM
ADS6124 12-Bit, 105-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device) - Evaluation Modules & Boards: ADS6144EVM
ADS6144 14-Bit, 105-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS6142EVM
ADS6142 14-Bit, 65-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS6125EVM
ADS6125 12-Bit, 125-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Dual Purposes: Data Buffer, The Other Face of CDCP1803PDF, 462 Kb, File published: Aug 13, 2004
The CDCP1803 is a clock driver by design, but can be used as a data buffer. The CDCP1803 performance as a data buffer is demonstrated both in terms of the bit errorrate (BER) and eye pattern diagrams. The CDCP1803 is tested over several signaling rates and different PRBS patterns.
Model Line
Series: CDCP1803 (6)
- CDCP1803RGER CDCP1803RGERG4 CDCP1803RGET CDCP1803RGETG4 CDCP1803RTHR CDCP1803RTHT
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Dividers
