Datasheet Texas Instruments CDCV850DGGRG4

2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85

Datasheets

PDF, 798 Kb, Revision: D, File published: Apr 10, 2013

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)	30 ps
Number of Outputs	10
Operating Frequency Range(Max)	140 MHz
Operating Frequency Range(Min)	60 MHz
Operating Temperature Range	-40 to 85 C
Package Group	TSSOP
Package Size: mm2:W x L	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG
Rating	Catalog
VCC	2.5 V
t(phase error)	180 ps
tsk(o)	75 ps

RoHS

Compliant

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HSTL Clock Buffer Using the CDCV850
PDF, 35 Kb, File published: Jul 15, 2002
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Using CDC857/CDCV850 toTransform Single-End CLK Signal Into Differential Output
PDF, 437 Kb, File published: Sep 27, 2000
The CDC857 and the CDCV850 devices are PLL-based differential clock drivers with a maximum operational frequency of 167 MHz. These devices have been designed to support a double-data-rate (DDR) specification and, therefore, they have higher immunity against incoupling common mode noise. However, they require a differential clock input signal.This report shows (a) how to convert a single ended cl

Series: CDCV850 (6)