Datasheet Texas Instruments CDCV850

Manufacturer	Texas Instruments
Series	CDCV850

2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface

Datasheets

PDF, 798 Kb, Revision: D, File published: Apr 10, 2013

Extract from the document

	CDCV850DGG	CDCV850DGGG4	CDCV850DGGR	CDCV850DGGRG4	CDCV850IDGG	CDCV850IDGGG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	NRND (Not recommended for new designs)	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No

	CDCV850DGG	CDCV850DGGG4	CDCV850DGGR	CDCV850DGGRG4	CDCV850IDGG	CDCV850IDGGG4
N	1	2	3	4	5	6
Pin	48	48	48	48	48	48
Package Type	DGG	DGG	DGG	DGG	DGG	DGG
Industry STD Term	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	40	40	2000	2000	40	40
Carrier	TUBE	TUBE	LARGE T&R	LARGE T&R	TUBE	TUBE
Device Marking	CDCV850	CDCV850	CDCV850	CDCV850	CDCV850-I	CDCV850-I
Width (mm)	6.1	6.1	6.1	6.1	6.1	6.1
Length (mm)	12.5	12.5	12.5	12.5	12.5	12.5
Thickness (mm)	1.15	1.15	1.15	1.15	1.15	1.15
Pitch (mm)	.5	.5	.5	.5	.5	.5
Max Height (mm)	1.2	1.2	1.2	1.2	1.2	1.2
Mechanical Data	Download	Download	Download	Download	Download	Download

Parameters / Models	CDCV850DGG	CDCV850DGGG4	CDCV850DGGR	CDCV850DGGRG4	CDCV850IDGG	CDCV850IDGGG4
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps	30	30	30	30	30	30
Number of Outputs	10	10	10	10	10	10
Operating Frequency Range(Max), MHz	140	140	140	140	140	140
Operating Frequency Range(Min), MHz	60	60	60	60	60	60
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Package Group	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
VCC, V	2.5	2.5	2.5	2.5	2.5	2.5
t(phase error), ps	180	180	180	180	180	180
tsk(o), ps	75	75	75	75	75	75

	CDCV850DGG	CDCV850DGGG4	CDCV850DGGR	CDCV850DGGRG4	CDCV850IDGG	CDCV850IDGGG4
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

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HSTL Clock Buffer Using the CDCV850
PDF, 35 Kb, File published: Jul 15, 2002
The demand for driving 1.5-V HSTL signals for high-integrated and low-voltage digital logic is increasing. Most current systems use LVDS, LVPECL, or 2.5-V LVCMOSsignaling levels. Therefore, a solution is needed to convert these clock signals into HSTL signal swing.The purpose this report is to show how to generate an HSTL compliant clock signal using the CDCV850. This clock buffer accepts LV
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Using CDC857/CDCV850 toTransform Single-End CLK Signal Into Differential Output
PDF, 437 Kb, File published: Sep 27, 2000
The CDC857 and the CDCV850 devices are PLL-based differential clock drivers with a maximum operational frequency of 167 MHz. These devices have been designed to support a double-data-rate (DDR) specification and, therefore, they have higher immunity against incoupling common mode noise. However, they require a differential clock input signal.This report shows (a) how to convert a single ended cl

Series: CDCV850 (6)