Datasheet Texas Instruments CDCVF855PWG4
| Manufacturer | Texas Instruments |
| Series | CDCVF855 |
| Part Number | CDCVF855PWG4 |
2.5V Phase Lock Loop DDR Clock Driver 28-TSSOP
Datasheets
1.5-V Phase-Lock Loop Clock Driver datasheet
PDF, 788 Kb, Revision: A, File published: May 3, 2007
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 28 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 50 |
| Carrier | TUBE |
| Device Marking | CDCVF855 |
| Width (mm) | 4.4 |
| Length (mm) | 9.7 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 65 ps |
| Number of Outputs | 4 |
| Operating Frequency Range(Max) | 220 MHz |
| Operating Frequency Range(Min) | 60 MHz |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) PKG |
| Rating | Catalog |
| VCC | 2.5 V |
| t(phase error) | 50 ps |
| tsk(o) | 40 ps |
Eco Plan
| RoHS | Compliant |
Model Line
Series: CDCVF855 (4)
- CDCVF855PW CDCVF855PWG4 CDCVF855PWR CDCVF855PWRG4
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers
