Datasheet Texas Instruments CLC021AVGZ-3.3/NOPB

CLC021
www.ti.com SNLS068H – MAY 2000 – REVISED APRIL 2013 CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion
Check for Samples: CLC021 FEATURES APPLICATIONS 1 2 (1) SMPTE 259M Serial Digital Video Standard
Compliant
Supports All NTSC and PAL Standard
Component and Composite Serial Video Data
Rates
No External Serial Data Rate Setting or VCO
Filtering Components Required (1)
Fast VCO Lock Time: 500Ω). If the
Lock Detect output is to be externally monitored, the attached monitoring circuit should present a DC resistance
greater than 5 kΩ so as not to affect Lock Detect indicator operation. Connect LOCK DETECT to TPG ENABLE for test pattern generator function.
Remove RP1 & RP3 and replace RP2 & RP4 with 50Ω resistor packs for coax interfacing.
Install RP1-4 when using ribbon cable for input interfacing.
This board is designed for use with TTL power supplies only. Figure 10. SD021EVK Schematic Diagram 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021
www.ti.com SNLS068H – MAY 2000 – REVISED APRIL 2013 MEASURING JITTER
The test method used to obtain the timing jitter value given in the AC Electrical Specification table is based on
procedures and equipment described in SMPTE RP 192-1996. The recommended practice discusses several
methods and indicator devices. An FFT method performed by standard video test equipment was used to obtain
the data given in this data sheet. As such, the jitter characteristics (or jitter floor) of the measurement equipment,
particularly the measurement analyzer, become integral to the resulting jitter value. The method and equipment
were chosen so that the test can be easily duplicated by the design engineer using most standard digital video
test equipment. In so doing, similar results should be achieved. The intrinsic jitter floor of the CLC021's PLL is …