Datasheet Texas Instruments DAC38RF80IAAV
| Manufacturer | Texas Instruments |
| Series | DAC38RF80 |
| Part Number | DAC38RF80IAAV |
Dual-Channel, 14-Bit, 9-GSPS, 6x-24x Interpolating, 6 & 9 GHz PLL Digital-to-Analog Converter (DAC) 144-FCBGA -40 to 85
Datasheets
DAC38RFxx Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL datasheet
PDF, 3.7 Mb, Revision: C, File published: Jul 31, 2017
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 144 |
| Package Type | AAV |
| Industry STD Term | FCBGA |
| JEDEC Code | S-PBGA-N |
| Package QTY | 168 |
| Carrier | JEDEC TRAY (5+1) |
| Device Marking | DAC38RF80I |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1.45 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.94 |
| Mechanical Data | Download |
Parametrics
| Architecture | Current Source |
| DAC Channels | 2 |
| Interface | JESD204B |
| Interpolation | 6x,8x,10x,12x,16x,18x,20x,24x |
| Operating Temperature Range | -40 to 85 C |
| Package Group | FCBGA |
| Package Size: mm2:W x L | See datasheet (FCBGA) PKG |
| Power Consumption(Typ) | 3800 mW |
| Rating | Catalog |
| Resolution | 14 Bits |
| SFDR | 72 dB |
| Sample / Update Rate | 9000 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: TSW40RF80EVM
2T2R RF-Sampling Transceiver With Dual 14-Bit 3GSPS ADC, Dual 14-Bit 9GSPS DAC and Clocking Solution
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: DAC38RF80EVM
DAC38RF80 Dual-Channel, 14-Bit, 9-GSPS, 6x-24x Interpolating, 6 & 9 GHz PLL DAC Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- RF Sampling DAC with 800 MHz of IBW LTEPDF, 673 Kb, File published: Oct 28, 2016
- Digital RF Power Control for Power Amplifer Protection in Wireless BasePDF, 1.4 Mb, File published: Feb 6, 2017
- DAC38RF8x Test ModesPDF, 3.0 Mb, File published: Jul 25, 2017
The DAC38RF8x family of devices comes equipped with multiple test modes to assist users in verifying systems in rapid prototyping situations. This application report covers two of the available tests, the pseudorandom binary-sequence test and JESD204B short pattern test, in detail using the TI DAC38RF8xEVM and TSW14J56EVM capture card. - Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer InformationPDF, 600 Kb, File published: Aug 2, 2017
Input/output Buffer Information Specification (IBIS) models are used to simulate digital electrical interfaces.These models can be categorized into two main categories: traditional and algorithmic modeling interface(AMI). AMI is typically used for SerDes channel simulation, and is different from the traditional IBIS model,which is the focus of this document. These models are simple ASCII tex - Eye Scan Testing with the DAC38RFxxPDF, 3.6 Mb, File published: Aug 10, 2017
The DAC38RFxx family of devices comes equipped with the capability to generate eye diagrams by usinging JTAG communication with the DAC38RF8x eye scan GUI software. By running this software, users can generate eye diagrams to compare with the JESD204B standard eye mask requirements, and verify signal integrity performance of the SerDes link between DAC and FPGA/ASIC. This application report descri
Model Line
Series: DAC38RF80 (2)
- DAC38RF80IAAV DAC38RF80IAAVR
Manufacturer's Classification
- Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)
