Datasheet Texas Instruments DAC38RF97IAAVR
| Manufacturer | Texas Instruments |
| Series | DAC38RF97 |
| Part Number | DAC38RF97IAAVR |
Dual-Channel, 14-Bit, 6-GSPS, 12x-24x Interpolating, 6-GHz GSM PLL Digital-to-Analog Converter (DAC) 144-FCBGA -40 to 85
Datasheets
DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL datasheet
PDF, 3.5 Mb, Revision: B, File published: Jul 31, 2017
Extract from the document
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 144 |
| Package Type | AAV |
| Industry STD Term | FCBGA |
| JEDEC Code | S-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | DAC38RF97I |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1.45 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.94 |
| Mechanical Data | Download |
Parametrics
| Architecture | Current Source |
| DAC Channels | 2 |
| Interface | JESD204B |
| Interpolation | 12x,16x,18x,20x,24x |
| Operating Temperature Range | -40 to 85 C |
| Package Group | FCBGA |
| Package Size: mm2:W x L | See datasheet (FCBGA) PKG |
| Power Consumption(Typ) | 3800 mW |
| Rating | Catalog |
| Resolution | 14 Bits |
| SFDR | 72 dB |
| Sample / Update Rate | 6200 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: DAC38RF87EVM
DAC38RF87 Dual-Channel, 14-Bit, 6.2-GSPS, 6x-24x Interpolating, 6-GHz GSM PLL DAC Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- DAC38RF8x Test ModesPDF, 3.0 Mb, File published: Jul 25, 2017
The DAC38RF8x family of devices comes equipped with multiple test modes to assist users in verifying systems in rapid prototyping situations. This application report covers two of the available tests, the pseudorandom binary-sequence test and JESD204B short pattern test, in detail using the TI DAC38RF8xEVM and TSW14J56EVM capture card. - Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer InformationPDF, 600 Kb, File published: Aug 2, 2017
Input/output Buffer Information Specification (IBIS) models are used to simulate digital electrical interfaces.These models can be categorized into two main categories: traditional and algorithmic modeling interface(AMI). AMI is typically used for SerDes channel simulation, and is different from the traditional IBIS model,which is the focus of this document. These models are simple ASCII tex - Eye Scan Testing with the DAC38RFxxPDF, 3.6 Mb, File published: Aug 10, 2017
The DAC38RFxx family of devices comes equipped with the capability to generate eye diagrams by usinging JTAG communication with the DAC38RF8x eye scan GUI software. By running this software, users can generate eye diagrams to compare with the JESD204B standard eye mask requirements, and verify signal integrity performance of the SerDes link between DAC and FPGA/ASIC. This application report descri
Model Line
Series: DAC38RF97 (2)
- DAC38RF97IAAV DAC38RF97IAAVR
Manufacturer's Classification
- Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)
