Datasheet Texas Instruments DAC5672A

Manufacturer	Texas Instruments
Series	DAC5672A

Datasheets

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Status

Packaging

Parametrics

Parameters / Models	DAC5672AIPFB	DAC5672AIPFBR
Architecture	Current Source	Current Source
DAC Channels	2	2
Interface	Parallel CMOS	Parallel CMOS
Interpolation	1x	1x
Operating Temperature Range, C	-40 to 85	-40 to 85
Package Group	TQFP	TQFP
Package Size: mm2:W x L, PKG	48TQFP: 81 mm2: 9 x 9(TQFP)	48TQFP: 81 mm2: 9 x 9(TQFP)
Power Consumption(Typ), mW	330	330
Rating	Catalog	Catalog
Resolution, Bits	14	14
SFDR, dB	84	84
Sample / Update Rate, MSPS	275	275

Eco Plan

Application Notes

• Download
  High Speed Digital-to-Analog Converters Basics (Rev. A)
  PDF, 829 Kb, Revision: A, File published: Oct 23, 2012
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Model Line

Manufacturer's Classification

• Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)