Datasheet Texas Instruments DAC5675
| Manufacturer | Texas Instruments |
| Series | DAC5675 |
14-Bit, 400-MSPS Digital-to-Analog Converter (DAC)
Datasheets
DAC5675: 14-Bit, 400-MSPS Digital-To-Analog Converter datasheet
PDF, 576 Kb, Revision: C, File published: Aug 27, 2004
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Prices
Status
| DAC5675IPHP | DAC5675IPHPR | DAC5675IPHPRG4 | |
|---|---|---|---|
| Lifecycle Status | NRND (Not recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No | No |
Packaging
| DAC5675IPHP | DAC5675IPHPR | DAC5675IPHPRG4 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 48 | 48 | 48 |
| Package Type | PHP | PHP | PHP |
| Industry STD Term | HTQFP | HTQFP | HTQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 250 | ||
| Carrier | JEDEC TRAY (10+1) | ||
| Device Marking | DAC5675I | ||
| Width (mm) | 7 | 7 | 7 |
| Length (mm) | 7 | 7 | 7 |
| Thickness (mm) | 1 | 1 | 1 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download |
Eco Plan
| DAC5675IPHP | DAC5675IPHPR | DAC5675IPHPRG4 | |
|---|---|---|---|
| RoHS | Compliant | Not Compliant | Not Compliant |
| Pb Free | No | No |
Application Notes
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Superposition: The Hidden DAC Linearity ErrorPDF, 106 Kb, File published: Oct 2, 2000
A digital-to analog converter (DAC) translates digital signals to analog signals. For example, a 12-bit DAC takes a 12-bit binary number, called an input code, and converts it into one of 4,096 analog output voltages or currents. When the contribution to the output voltage or current of each individual bit is independent of any other, it means that the device exhibits no superposition error or tha
Model Line
Series: DAC5675 (3)
Manufacturer's Classification
- Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)
