Datasheet Texas Instruments DAC5687

Manufacturer	Texas Instruments
Series	DAC5687

Dual-Channel, 16-Bit, 500-MSPS, 1x-8x Interpolating Digital-to-Analog Converter (DAC)

Datasheets

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PDF, 2.7 Mb, Revision: E, File published: Sep 20, 2006

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Status

	DAC5687IPZP	DAC5687IPZPG4	DAC5687IPZPR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes	No	Yes

Packaging

	DAC5687IPZP	DAC5687IPZPG4	DAC5687IPZPR
N	1	2	3
Pin	100	100	100
Package Type	PZP	PZP	PZP
Industry STD Term	HTQFP	HTQFP	HTQFP
JEDEC Code	S-PQFP-G	S-PQFP-G	S-PQFP-G
Package QTY	90	90	1000
Carrier	EIAJ TRAY (10+1)	EIAJ TRAY (10+1)	LARGE T&R
Device Marking	DAC5687IPZP	DAC5687IPZP	DAC5687IPZP
Width (mm)	14	14	14
Length (mm)	14	14	14
Thickness (mm)	1	1	1
Pitch (mm)	.5	.5	.5
Max Height (mm)	1.2	1.2	1.2
Mechanical Data	Download	Download	Download

Parametrics

Parameters / Models	DAC5687IPZP	DAC5687IPZPG4	DAC5687IPZPR
Architecture	Current Sink	Current Sink	Current Sink
DAC Channels	2	2	2
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS
Interpolation	1x,2x,4x,8x	1x,2x,4x,8x	1x,2x,4x,8x
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Package Group	HTQFP	HTQFP	HTQFP
Package Size: mm2:W x L, PKG	100HTQFP: 256 mm2: 16 x 16(HTQFP)	100HTQFP: 256 mm2: 16 x 16(HTQFP)	100HTQFP: 256 mm2: 16 x 16(HTQFP)
Power Consumption(Typ), mW	1410	1410	1410
Rating	Catalog	Catalog	Catalog
Resolution, Bits	16	16	16
SFDR, dB	80	80	80
Sample / Update Rate, MSPS	500	500	500

Eco Plan

	DAC5687IPZP	DAC5687IPZPG4	DAC5687IPZPR
RoHS	Compliant	Compliant	Compliant

Application Notes

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DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)
PDF, 686 Kb, Revision: A, File published: Jul 21, 2005
DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes
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Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
PDF, 319 Kb, File published: Jul 14, 2009
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Passive Terminations for Current Output DACs
PDF, 244 Kb, File published: Nov 10, 2008
The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
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Q3 2009 Issue Analog Applications Journal
PDF, 2.1 Mb, File published: Jul 14, 2009
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High Speed Digital-to-Analog Converters Basics (Rev. A)
PDF, 829 Kb, Revision: A, File published: Oct 23, 2012
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Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
PDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Model Line

Series: DAC5687 (3)

DAC5687IPZP DAC5687IPZPG4 DAC5687IPZPR

Manufacturer's Classification

Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)