Datasheet Texas Instruments DP83867IRPAPT
| Manufacturer | Texas Instruments |
| Series | DP83867IR |
| Part Number | DP83867IRPAPT |
Gigabit Ethernet PHY Customized for Harsh Industrial Environments 64-HTQFP -40 to 85
Datasheets
DP83867IR/CR Robust, High Immunity 10/100/1000 Ethernet Physical Layer Transceiver datasheet
PDF, 1.7 Mb, Revision: E, File published: Mar 14, 2017
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 64 |
| Package Type | PAP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | DP83867IR |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Cable Length | 130 m |
| Datarate | 10/100/1000 Mbps |
| Function | PHY |
| Interface | GMII,RGMII,MII |
| JTAG1149.1 | Yes |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 64HTQFP: 144 mm2: 12 x 12(HTQFP) PKG |
| Port Count | Single |
| Rating | Catalog |
| Special Features | Cable Diagnostics,IEEE 1588 SOF |
| Supply Voltage | 1.1,2.5 Volt |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: DP83867IRPAP-EVM
DP83867IRPAP-EVM 1000M/100M/10M Ethernet PHY Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: DP83867ERGZ-R-EVM
DP83867ERGZ RGMII 1000M/100M/10M Ethernet PHY Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: K2GICE
66AK2Gx (K2G) Industrial Communications Engine (ICE)
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: EVMX777BG-01-00-00
J6Entry, RSP and TDA2E-17 CPU Board Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: EVMX777G-01-20-00
J6Entry/RSP Infotainment (CPU+Display+JAMR3) Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- DP83867IRPAP Power Consumption DataPDF, 72 Kb, File published: Aug 27, 2015
Power consumption on an Ethernet PHY is affected by different operating conditions. System design around Ethernet products requires accurate power consumption numbers for component selection, thermal management and power distribution planning. This application report details power consumption of DP83867 in different conditions. - Importance of Latency in Factory AutomationPDF, 196 Kb, File published: Oct 25, 2015
Latency is a critical parameter in Ethernet networks developed for Factory Automation applications. Latency is not a defined value for Ethernet as specified by the IEEE 802.3 standard. Nor is Ethernet inherently synchronous or repeatable. This disconnect between the inherent characteristics of Ethernet and the needs of Factory Automation applications must be bridged though care - RGMII Interface Timing BudgetsPDF, 185 Kb, File published: Oct 28, 2015
RGMII Interface Timing Budgets is intended to serve as a guideline for developing a timing budget when using the RGMII v1.3 and v2.0 standard with a Gigabit PHY transceiver like the DP83867. - DP83867 Troubleshooting Guide (Rev. A)PDF, 700 Kb, Revision: A, File published: Apr 6, 2016
A 10/100/1000 Ethernet Physical Layer device has multiple connections and many possible configurationoptions. While the DP83867 is designed with a priority on ease of use, there are many factors to considerduring initial board bring up. This application note provides guidance on the key criteria to verify in order toexpedite initial validation of DP83867 applications. - DP83867E/IS/CS/IR/CR RGZ Power Consumption DataPDF, 92 Kb, File published: Oct 7, 2015
Power consumption on an Ethernet PHY is affected by different operating conditions. System design around Ethernet products requires accurate power consumption numbers for component selection, thermal management and power distribution planning. This application report details power consumption of DP83867 in different conditions. - How to Configure DP83867 Start of FramePDF, 78 Kb, File published: Oct 27, 2015
The DP83867 can detect a Start of Frame Delimiter (SFD) for transmit and receive packets and output a pulse via a GPIO that can be used to assess the latency of the link between the DP83867 and a timestamp capable partner. For real-time systems and systems implementing the IEEE 1588 Precision Time Protocol (PTP) to timestamp packets for synchronizing devices across the network, - How to Configure DP838XX for Ethernet Compliance and Loopback Testing (Rev. A)PDF, 820 Kb, Revision: A, File published: Jan 31, 2017
This application report covers how to setup and configure the DP838xx PHY (using the customer EVM) forEthernet Physical Layer Compliance (IEEE 802.3) testing as the device under test (DUT). This applicationnote primarily uses DP83867 as an example, but any DP838xx can use these procedures for compliancetesting.Refer to DP83822 IEEE 802.3u Compliance and Debug (SNLA266) for a DP83822 specif
Model Line
Series: DP83867IR (4)
- DP83867IRPAPR DP83867IRPAPT DP83867IRRGZR DP83867IRRGZT
Manufacturer's Classification
- Semiconductors > Interface > Ethernet > Ethernet PHY
