Datasheet Texas Instruments DS90CF364A
| Manufacturer | Texas Instruments |
| Series | DS90CF364A |
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz
Datasheets
DS90CF384A/364A 3.3V LVDS Rcvr 24Bit FPD Link 65MHz/18Bit FPD Link - 65 MHz datasheet
PDF, 1.4 Mb, Revision: I, File published: Apr 19, 2013
Extract from the document
Prices
Status
| DS90CF364AMTD | DS90CF364AMTD/NOPB | DS90CF364AMTDX | DS90CF364AMTDX/NOPB | |
|---|---|---|---|---|
| Lifecycle Status | NRND (Not recommended for new designs) | Active (Recommended for new designs) | NRND (Not recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | No | No |
Packaging
| DS90CF364AMTD | DS90CF364AMTD/NOPB | DS90CF364AMTDX | DS90CF364AMTDX/NOPB | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 48 | 48 | 48 | 48 |
| Package Type | DGG | DGG | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 38 | 38 | 1000 | 1000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | >B | >B | >B | >B |
| Width (mm) | 6.1 | 6.1 | 6.1 | 6.1 |
| Length (mm) | 12.5 | 12.5 | 12.5 | 12.5 |
| Thickness (mm) | 1.15 | 1.15 | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | DS90CF364AMTD | DS90CF364AMTD/NOPB | DS90CF364AMTDX | DS90CF364AMTDX/NOPB |
|---|---|---|---|---|
| Color Depth, bpp | 18 | 18 | 18 | 18 |
| Function | Receiver | Receiver | Receiver | Receiver |
| Input Compatibility | FPD-Link LVDS | FPD-Link LVDS | FPD-Link LVDS | FPD-Link LVDS |
| Operating Temperature Range, C | -10 to 70 | -10 to 70 | -10 to 70 | -10 to 70 |
| Output Compatibility | LVCMOS,LVTTL | LVCMOS,LVTTL | LVCMOS,LVTTL | LVCMOS,LVTTL |
| Package Group | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) |
| Pixel Clock Min, MHz | 20 | 20 | 20 | 20 |
| Pixel Clock(Max), MHz | 65 | 65 | 65 | 65 |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Total Throughput, Mbps | 1300 | 1300 | 1300 | 1300 |
Eco Plan
| DS90CF364AMTD | DS90CF364AMTD/NOPB | DS90CF364AMTDX | DS90CF364AMTDX/NOPB | |
|---|---|---|---|---|
| RoHS | See ti.com | Compliant | See ti.com | Compliant |
Application Notes
- AN-1056 STN Application Using FPD-LinkPDF, 85 Kb, File published: May 14, 2004
Application Note 1056 STN Application Using FPD-Link - TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color MapPDF, 52 Kb, File published: May 15, 2004
Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map - LVDS Display Interface (LDI) TFT Data Mapping for Interoperability w/FPD-LinkPDF, 65 Kb, File published: May 14, 2004
Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperabil ity with FPD-Link - AN-1085 FPD-Link PCB and Interconnect Design-In GuidelinesPDF, 344 Kb, File published: May 14, 2004
Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines - Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
- AN-1032 An Introduction to FPD-Link (Rev. C)PDF, 185 Kb, Revision: C, File published: Aug 8, 2017
The FPD-Linkchipsetarchitecturein conjunctionwith the LVDStechnologyprovidesthe highbandwidthinterfacenecessaryfor leadingedgedisplaytechnology.The conversionfromparallelTTL to serialLVDSallowsfor a narrowinterfacebetweengraphicscontrollerand panel.A narrowerinterfacemeanslowercablecost and simplifiesthe physicalconnectionthroug
Model Line
Series: DS90CF364A (4)
Manufacturer's Classification
- Semiconductors> Interface> Display & Imaging SerDes> FlatLink/FPD-Link (LVDS for LCD)
