Datasheet Texas Instruments DS90CF384MTDX/NOPB
| Manufacturer | Texas Instruments |
| Series | DS90CF384 |
| Part Number | DS90CF384MTDX/NOPB |
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz 56-TSSOP -40 to 85
Datasheets
DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display datasheet
PDF, 380 Kb, File published: May 13, 2004
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 56 | 56 |
| Package Type | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 1000 | 1000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | DS90CF384MTD | >B |
| Width (mm) | 6.1 | 6.1 |
| Length (mm) | 14 | 14 |
| Thickness (mm) | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
Parametrics
| Color Depth | 24 bpp |
| Function | Receiver |
| Input Compatibility | FPD-Link LVDS |
| Operating Temperature Range | -40 to 85 C |
| Output Compatibility | LCMOS,LVTTL |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) PKG |
| Pixel Clock Min | 20 MHz |
| Pixel Clock(Max) | 65 MHz |
| Rating | Catalog |
| Total Throughput | 1800 Mbps |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: FLINK3V8BT-85
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- AN-1056 STN Application Using FPD-LinkPDF, 85 Kb, File published: May 14, 2004
Application Note 1056 STN Application Using FPD-Link - TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color MapPDF, 52 Kb, File published: May 15, 2004
Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map - LVDS Display Interface (LDI) TFT Data Mapping for Interoperability w/FPD-LinkPDF, 65 Kb, File published: May 14, 2004
Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperabil ity with FPD-Link - AN-1085 FPD-Link PCB and Interconnect Design-In GuidelinesPDF, 344 Kb, File published: May 14, 2004
Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines - Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
- AN-1032 An Introduction to FPD-Link (Rev. C)PDF, 185 Kb, Revision: C, File published: Aug 8, 2017
The FPD-Linkchipsetarchitecturein conjunctionwith the LVDStechnologyprovidesthe highbandwidthinterfacenecessaryfor leadingedgedisplaytechnology.The conversionfromparallelTTL to serialLVDSallowsfor a narrowinterfacebetweengraphicscontrollerand panel.A narrowerinterfacemeanslowercablecost and simplifiesthe physicalconnectionthroug
Model Line
Series: DS90CF384 (2)
- DS90CF384MTD/NOPB DS90CF384MTDX/NOPB
Manufacturer's Classification
- Semiconductors > Interface > FPD-Link SerDes > Display SerDes
