Datasheet Texas Instruments DS90CR218A

ManufacturerTexas Instruments
SeriesDS90CR218A
Datasheet Texas Instruments DS90CR218A

+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 85 MHz

Datasheets

DS90CR218A 3.3VRising Edge Data Strobe LVDS 21Bit Chan Link 12MHz to 85MHz datasheet
PDF, 903 Kb, Revision: D, File published: Apr 22, 2013
Extract from the document

Prices

Status

DS90CR218AMTD/NOPBDS90CR218AMTDX/NOPB
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNo

Packaging

DS90CR218AMTD/NOPBDS90CR218AMTDX/NOPB
N12
Pin4848
Package TypeDGGDGG
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY381000
CarrierTUBELARGE T&R
Device MarkingDS90CR218AMTDDS90CR218AMTD
Width (mm)6.16.1
Length (mm)12.512.5
Thickness (mm)1.151.15
Pitch (mm).5.5
Max Height (mm)1.21.2
Mechanical DataDownloadDownload

Parametrics

Parameters / ModelsDS90CR218AMTD/NOPB
DS90CR218AMTD/NOPB
DS90CR218AMTDX/NOPB
DS90CR218AMTDX/NOPB
Clock Max, MHz8585
Clock Min, MHz1212
Compression Ratio21 to 321 to 3
Data Throughput, Mbps17851785
ESD, kV77
FunctionDeserializerDeserializer
Input CompatibilityLVDSLVDS
Operating Temperature Range, C-10 to 70-10 to 70
Output CompatibilityLVCMOSLVCMOS
Package GroupTSSOPTSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Parallel Bus Width, bits2121
ProtocolsChannel-Link IChannel-Link I
RatingCatalogCatalog
Supply Voltage(s), V3.33.3

Eco Plan

DS90CR218AMTD/NOPBDS90CR218AMTDX/NOPB
RoHSCompliantCompliant

Application Notes

  • CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications
    PDF, 269 Kb, File published: Oct 5, 1998
  • AN-1538 Interfacing Nationals DS90CR218A and LM98714 (Rev. C)
    PDF, 84 Kb, Revision: C, File published: Apr 26, 2013
    This application report examines the issues that system designers may face when interfacing the Texas Instruments DS90CR218A and LM98714. It also offers guidance and solutions on solving these issues that will deliver for a reliable and cost effective LVDS data link.
  • Multi-Drop Channel-Link Operation
    PDF, 212 Kb, File published: Oct 4, 2004
  • Receiver Skew Margin for Channel Link I and FPD Link I Devices
    PDF, 418 Kb, File published: Jan 13, 2016
  • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines
    PDF, 245 Kb, File published: May 15, 2004
    Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines

Model Line

Manufacturer's Classification

  • Semiconductors> Interface> Serializer, Deserializer> Channel Link I