Datasheet Texas Instruments DS90CR285
| Manufacturer | Texas Instruments |
| Series | DS90CR285 |
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel - 66 MHz
Datasheets
DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28Bit Channel Link- 66MHz datasheet
PDF, 1.5 Mb, Revision: C, File published: Mar 5, 2013
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Prices
Status
| DS90CR285MTD | DS90CR285MTD/NOPB | DS90CR285MTDX | DS90CR285MTDX/NOPB | |
|---|---|---|---|---|
| Lifecycle Status | NRND (Not recommended for new designs) | Active (Recommended for new designs) | NRND (Not recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | Yes |
Packaging
| DS90CR285MTD | DS90CR285MTD/NOPB | DS90CR285MTDX | DS90CR285MTDX/NOPB | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 56 | 56 | 56 | 56 |
| Package Type | DGG | DGG | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 34 | 34 | 1000 | 1000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | DS90CR285MTD | >B | >B | >B |
| Width (mm) | 6.1 | 6.1 | 6.1 | 6.1 |
| Length (mm) | 14 | 14 | 14 | 14 |
| Thickness (mm) | 1.15 | 1.15 | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | DS90CR285MTD | DS90CR285MTD/NOPB | DS90CR285MTDX | DS90CR285MTDX/NOPB |
|---|---|---|---|---|
| Clock Max, MHz | 66 | 66 | 66 | 66 |
| Clock Min, MHz | 20 | 20 | 20 | 20 |
| Compression Ratio | 28 to 4 | 28 to 4 | 28 to 4 | 28 to 4 |
| Data Throughput, Mbps | 1848 | 1848 | 1848 | 1848 |
| ESD, kV | 7 | 7 | 7 | 7 |
| Function | Serializer | Serializer | Serializer | Serializer |
| Input Compatibility | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Compatibility | LVDS | LVDS | LVDS | LVDS |
| Package Group | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) |
| Parallel Bus Width, bits | 28 | 28 | 28 | 28 |
| Protocols | Channel-Link I | Channel-Link I | Channel-Link I | Channel-Link I |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Supply Voltage(s), V | 3.3 | 3.3 | 3.3 | 3.3 |
Eco Plan
| DS90CR285MTD | DS90CR285MTD/NOPB | DS90CR285MTDX | DS90CR285MTDX/NOPB | |
|---|---|---|---|---|
| RoHS | See ti.com | Compliant | See ti.com | Compliant |
Application Notes
- Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)PDF, 62 Kb, Revision: A, File published: Apr 26, 2013
This application note discusses how system designers are able to use Channel Link II ser/Des to improve old and new channel link designs. - CHANNEL LINK Moving and Shaping Information In Point-To-Point ApplicationsPDF, 269 Kb, File published: Oct 5, 1998
- Multi-Drop Channel-Link OperationPDF, 212 Kb, File published: Oct 4, 2004
- AN-1108 Channel-Link PCB and Interconnect Design-In GuidelinesPDF, 245 Kb, File published: May 15, 2004
Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines - Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
Model Line
Series: DS90CR285 (4)
Manufacturer's Classification
- Semiconductors> Interface> Serializer, Deserializer> Channel Link I
