Datasheet Texas Instruments DS90CR286A

ManufacturerTexas Instruments
SeriesDS90CR286A
Datasheet Texas Instruments DS90CR286A

+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link - 66 MHz

Datasheets

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz datasheet
PDF, 2.4 Mb, Revision: H, File published: Jan 18, 2016
Extract from the document

Prices

Status

DS90CR286AMTDDS90CR286AMTD/NOPBDS90CR286AMTDX/NOPB
Lifecycle StatusNRND (Not recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoYes

Packaging

DS90CR286AMTDDS90CR286AMTD/NOPBDS90CR286AMTDX/NOPB
N123
Pin565656
Package TypeDGGDGGDGG
Industry STD TermTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY34341000
CarrierTUBETUBELARGE T&R
Device Marking>BDS90CR286AMTD>B
Width (mm)6.16.16.1
Length (mm)141414
Thickness (mm)1.151.151.15
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical DataDownloadDownloadDownload

Parametrics

Parameters / ModelsDS90CR286AMTD
DS90CR286AMTD
DS90CR286AMTD/NOPB
DS90CR286AMTD/NOPB
DS90CR286AMTDX/NOPB
DS90CR286AMTDX/NOPB
Clock Max, MHz666666
Clock Min, MHz202020
Compression Ratio28 to 428 to 428 to 4
Data Throughput, Mbps184818481848
ESD, kV777
FunctionDeserializerDeserializerDeserializer
Input CompatibilityLVDSLVDSLVDS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output CompatibilityLVCMOSLVCMOSLVCMOS
Package GroupTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)
Parallel Bus Width, bits282828
ProtocolsChannel-Link IChannel-Link IChannel-Link I
RatingCatalogCatalogCatalog
Supply Voltage(s), V3.33.33.3

Eco Plan

DS90CR286AMTDDS90CR286AMTD/NOPBDS90CR286AMTDX/NOPB
RoHSSee ti.comCompliantCompliant

Application Notes

  • CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications
    PDF, 269 Kb, File published: Oct 5, 1998
  • Multi-Drop Channel-Link Operation
    PDF, 212 Kb, File published: Oct 4, 2004
  • Receiver Skew Margin for Channel Link I and FPD Link I Devices
    PDF, 418 Kb, File published: Jan 13, 2016
  • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines
    PDF, 245 Kb, File published: May 15, 2004
    Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines

Model Line

Manufacturer's Classification

  • Semiconductors> Interface> Serializer, Deserializer> Channel Link I