Datasheet Texas Instruments DS90CR286A-Q1
| Manufacturer | Texas Instruments |
| Series | DS90CR286A-Q1 |
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link - 66 MHz
Datasheets
DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz datasheet
PDF, 2.4 Mb, Revision: H, File published: Jan 18, 2016
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Prices
Status
| DS90CR286AQMT/NOPB | DS90CR286AQMTX/NOPB | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes |
Packaging
| DS90CR286AQMT/NOPB | DS90CR286AQMTX/NOPB | |
|---|---|---|
| N | 1 | 2 |
| Pin | 56 | 56 |
| Package Type | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 34 | 1000 |
| Carrier | TUBE | LARGE T&R |
| Device Marking | MT | MT |
| Width (mm) | 6.1 | 6.1 |
| Length (mm) | 14 | 14 |
| Thickness (mm) | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | DS90CR286AQMT/NOPB | DS90CR286AQMTX/NOPB |
|---|---|---|
| Clock Max, MHz | 66 | 66 |
| Clock Min, MHz | 20 | 20 |
| Compression Ratio | 28 to 4 | 28 to 4 |
| Data Throughput, Mbps | 1848 | 1848 |
| ESD, kV | 7 | 7 |
| Function | Deserializer | Deserializer |
| Input Compatibility | LVDS | LVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Output Compatibility | LVCMOS | LVCMOS |
| Package Group | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) |
| Parallel Bus Width, bits | 28 | 28 |
| Protocols | Channel-Link I | Channel-Link I |
| Rating | Automotive | Automotive |
| Supply Voltage(s), V | 3.3 | 3.3 |
Eco Plan
| DS90CR286AQMT/NOPB | DS90CR286AQMTX/NOPB | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- CHANNEL LINK Moving and Shaping Information In Point-To-Point ApplicationsPDF, 269 Kb, File published: Oct 5, 1998
- Multi-Drop Channel-Link OperationPDF, 212 Kb, File published: Oct 4, 2004
- Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
- AN-1108 Channel-Link PCB and Interconnect Design-In GuidelinesPDF, 245 Kb, File published: May 15, 2004
Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines
Model Line
Series: DS90CR286A-Q1 (2)
Manufacturer's Classification
- Semiconductors> Interface> Serializer, Deserializer> Channel Link I
