Datasheet Texas Instruments DS90CR287MTDX/NOPB
| Manufacturer | Texas Instruments |
| Series | DS90CR287 |
| Part Number | DS90CR287MTDX/NOPB |
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Transmitter - 85 MHz 56-TSSOP -10 to 70
Datasheets
DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet
PDF, 1.5 Mb, Revision: G, File published: Mar 5, 2013
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 56 | 56 |
| Package Type | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 1000 | 1000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | >B | DS90CR287MTD |
| Width (mm) | 6.1 | 6.1 |
| Length (mm) | 14 | 14 |
| Thickness (mm) | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
Parametrics
| Clock Max | 85 MHz |
| Clock Min | 20 MHz |
| Compression Ratio | 28 to 4 |
| Data Throughput | 2380 Mbps |
| ESD | 7 kV |
| Function | Serializer |
| Input Compatibility | LVCMOS |
| Operating Temperature Range | -10 to 70 C |
| Output Compatibility | LVDS |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) PKG |
| Parallel Bus Width | 28 bits |
| Protocols | Channel-Link I |
| Rating | Catalog |
| Supply Voltage(s) | 3.3 V |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: FLINK3V8BT-85
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)PDF, 62 Kb, Revision: A, File published: Apr 26, 2013
This application note discusses how system designers are able to use Channel Link II ser/Des to improve old and new channel link designs. - CHANNEL LINK Moving and Shaping Information In Point-To-Point ApplicationsPDF, 269 Kb, File published: Oct 5, 1998
- Multi-Drop Channel-Link OperationPDF, 212 Kb, File published: Oct 4, 2004
- Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, File published: Jan 13, 2016
- AN-1108 Channel-Link PCB and Interconnect Design-In GuidelinesPDF, 245 Kb, File published: May 15, 2004
Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines
Model Line
Series: DS90CR287 (4)
- DS90CR287MTD DS90CR287MTD/NOPB DS90CR287MTDX/NOPB DS90CR287SLC/NOPB
Manufacturer's Classification
- Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link
