Datasheet Texas Instruments DS90CR287SLC/NOPB

ManufacturerTexas Instruments
SeriesDS90CR287
Part NumberDS90CR287SLC/NOPB
Datasheet Texas Instruments DS90CR287SLC/NOPB

+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Transmitter - 85 MHz 64-NFBGA

Datasheets

DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet
PDF, 1.5 Mb, Revision: G, File published: Mar 5, 2013
Extract from the document

Prices

Status

Lifecycle StatusNRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin646464
Package TypeNZCNZCNZC
Industry STD TermNFBGANFBGANFBGA
JEDEC CodeS-PBGA-NS-PBGA-NS-PBGA-N
Package QTY360360360
CarrierJEDEC TRAY (10+1)JEDEC TRAY (10+1)JEDEC TRAY (10+1)
Device MarkingDS90CR287>BSLC
Width (mm)888
Length (mm)888
Thickness (mm)1.41.41.4
Pitch (mm).8.8.8
Max Height (mm)1.51.51.5
Mechanical DataDownloadDownloadDownload

Parametrics

Clock Max85 MHz
Clock Min20 MHz
Compression Ratio28 to 4
Data Throughput2380 Mbps
ESD7 kV
FunctionSerializer
Input CompatibilityLVCMOS
Operating Temperature Range-10 to 70 C
Output CompatibilityLVDS
Package GroupTSSOP
Package Size: mm2:W x L56TSSOP: 113 mm2: 8.1 x 14(TSSOP) PKG
Parallel Bus Width28 bits
ProtocolsChannel-Link I
RatingCatalog
Supply Voltage(s)3.3 V

Eco Plan

RoHSCompliant

Design Kits & Evaluation Modules

  • Evaluation Modules & Boards: FLINK3V8BT-85
    Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)
    PDF, 62 Kb, Revision: A, File published: Apr 26, 2013
    This application note discusses how system designers are able to use Channel Link II ser/Des to improve old and new channel link designs.
  • CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications
    PDF, 269 Kb, File published: Oct 5, 1998
  • Multi-Drop Channel-Link Operation
    PDF, 212 Kb, File published: Oct 4, 2004
  • Receiver Skew Margin for Channel Link I and FPD Link I Devices
    PDF, 418 Kb, File published: Jan 13, 2016
  • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines
    PDF, 245 Kb, File published: May 15, 2004
    Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines

Model Line

Manufacturer's Classification

  • Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link