Datasheet Texas Instruments DS90UB954TRGZTQ1
| Manufacturer | Texas Instruments |
| Series | DS90UB954-Q1 |
| Part Number | DS90UB954TRGZTQ1 |
Dual 2MP FPD-Link III Deserializer With CSI-2 Outputs for 2MP/60fps Cameras and RADAR 48-VQFN -40 to 105
Datasheets
DS90UB954-Q1 Dual FPD-Link III Deserializer Hub With MIPI CSI-2 Outputs for 2MP/60fps Cameras and RADAR datasheet
PDF, 2.3 Mb, File published: Aug 22, 2017
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 48 |
| Package Type | RGZ |
| Industry STD Term | VQFN |
| JEDEC Code | S-PQFP-N |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | UB954Q |
| Width (mm) | 7 |
| Length (mm) | 7 |
| Thickness (mm) | .9 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1 |
| Mechanical Data | Download |
Parametrics
| Color Depth | 12 bpp |
| Diagnostics | BIST |
| Function | Deserializer |
| Input Compatibility | FPD-Link III LVDS |
| Operating Temperature Range | -40 to 105 C |
| Output Compatibility | MIPI CSI-2 |
| Package Group | VQFN |
| Package Size: mm2:W x L | 48VQFN: 49 mm2: 7 x 7(VQFN) PKG |
| Pixel Clock Min | 25 MHz |
| Pixel Clock(Max) | 100 MHz |
| Rating | Automotive |
| Signal Conditioning | Adaptive Equalizer,Programmable Equalizer |
| Total Throughput | 1866 Mbps |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: DS90UB954-Q1EVM
DS90UB954-Q1 FPD-Link III Camera Deserializer Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ALP
Analog LaunchPad Framework Utility
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Comparing Bus Solutions (Rev. C)PDF, 1.8 Mb, Revision: C, File published: Aug 8, 2017
The stronginterestin this applicationreportpromptedthis thirdedition.In additionto the changesandupdatesmadethroughoutthesesections,this editionalsodiscussesLocalInterconnectNetwork(LIN),USB-On-the-Go,DisplayPort,digitalisolators,and more.This applicationreportservesas a referencetoolfor findingthe mostappropriatedatabus solut - How to measure Total Jitter (TJ) (Rev. B)PDF, 6.2 Mb, Revision: B, File published: Aug 8, 2017
Today,the jitterspecification,TJ, is usedin moreandmoresystems,at the sametimethe jitterrequirementsget lowerand lower.Clockgeneratorsor jittercleanerslike the CDCM6208meetthosetoughjitterspecificationsfor mostsystems(for example,TMS320TCI66xxDSP-basedsystems;seeHardwareDesignGuidefor KeyStoneI Devices(SPRABI2).Theothers - High Speed Layout Guidelines (Rev. A)PDF, 762 Kb, Revision: A, File published: Aug 8, 2017
Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection - AN-1032 An Introduction to FPD-Link (Rev. C)PDF, 185 Kb, Revision: C, File published: Aug 8, 2017
The FPD-Linkchipsetarchitecturein conjunctionwith the LVDStechnologyprovidesthe highbandwidthinterfacenecessaryfor leadingedgedisplaytechnology.The conversionfromparallelTTL to serialLVDSallowsfor a narrowinterfacebetweengraphicscontrollerand panel.A narrowerinterfacemeanslowercablecost and simplifiesthe physicalconnectionthroug - LDO PSRR Measurement Simplified (Rev. A)PDF, 131 Kb, Revision: A, File published: Aug 9, 2017
This applicationreportexplainsdifferentmethodsof measuringthe PowerSupplyRejectionRatio(PSRR)of a Low-Dropout(LDO)regulatorand includesthe prosand consof thesemeasuringmethods - LDO Noise Demystified (Rev. A)PDF, 785 Kb, Revision: A, File published: Aug 9, 2017
Thisapplicationreportexplainsthe differencebetweennoiseand PSRRof an LDO.It also explainsthedifferentwaysnoiseis specifiedin LDOdatasheetsandwhichspecificationshouldbe usedin theapplication.Finallyit explainshow LDOnoiseis reduced.
Model Line
Series: DS90UB954-Q1 (2)
- DS90UB954TRGZRQ1 DS90UB954TRGZTQ1
Manufacturer's Classification
- Semiconductors > Interface > FPD-Link SerDes > Camera SerDes
