Datasheet Texas Instruments DS90UH926QSQE/NOPB
| Manufacturer | Texas Instruments |
| Series | DS90UH926Q-Q1 |
| Part Number | DS90UH926QSQE/NOPB |
5 - 85 MHz 24-bit Color FPD-Link III Deserializer with HDCP 60-WQFN -40 to 105
Datasheets
DS90UH926Q-Q1 720p, 24-Bit Color FPD-Link III Deserializer With HDCP datasheet
PDF, 1.4 Mb, Revision: M, File published: Aug 3, 2017
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 60 |
| Package Type | NKB |
| Industry STD Term | WQFN |
| JEDEC Code | S-PQSO-N |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | UH926QSQ |
| Width (mm) | 9 |
| Length (mm) | 9 |
| Thickness (mm) | .8 |
| Pitch (mm) | .5 |
| Max Height (mm) | .8 |
| Mechanical Data | Download |
Parametrics
| Color Depth | 24 bpp |
| Diagnostics | BIST |
| EMI Reduction | SSCG,Staggered Outputs |
| Function | Deserializer |
| Input Compatibility | FPD-Link III LVDS |
| Operating Temperature Range | -40 to 105 C |
| Output Compatibility | LVCMOS |
| Package Group | WQFN |
| Package Size: mm2:W x L | 60WQFN: 81 mm2: 9 x 9(WQFN) PKG |
| Pixel Clock Min | 5 MHz |
| Pixel Clock(Max) | 85 MHz |
| Rating | Automotive |
| Signal Conditioning | Adaptive Equalizer |
| Special Features | HDCP,I2C Config,I2S Audio |
| Total Throughput | 2550 Mbps |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: DS90UB928QEVM
DS90UB928QEVM FPD-Link III Deserializer Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: EVMX777G-01-20-00
J6Entry/RSP Infotainment (CPU+Display+JAMR3) Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: DS90UH926QSEVB
DS90UH926QSEVB Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: DS90UH928QEVM
DS90UH928QEVM FPD-Link III Deserializer Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- AN-2198 Exploring Int Test Patt Gen Feat of 720p FPD-Link III Devices (Rev. C)PDF, 105 Kb, Revision: C, File published: Jun 28, 2013
This application report describes the pattern generator feature of the FPD-Link III 720p devices(DS90Ux92xQ), including the relevant control registers. It also provides several examples for accessingthese control registers to meet custom display application requirements. - Using the I2S Audio Interface of DS90Ux92x FPD-Link III DevicesPDF, 121 Kb, File published: May 4, 2013
I2S is a standard protocol for transmitting two channels (stereo) Pulse Code Modulated digital data over a3-wire serial bus.Advanced automotive systems require transport of multiple audio data sources, such as mobile devices,Navigation systems, Infotainment, security, or gaming consoles, to speakers located throughout thevehicle. Also, surround sound systems requiring multiple audio data - I2C Communication Over FPD-Link III with Bidirectional Control Channel (Rev. A)PDF, 53 Kb, Revision: A, File published: Apr 26, 2013
This application note describes communication between devices using the FPD-Link III SerDes with a bidirectional control channel using I2C. The low latency bidirectional control interface allows the master I2C device to remotely control peripherals across the serial link. - Enabling GPIOs in DS90UB925 and DS90UB926PDF, 293 Kb, File published: Nov 10, 2015
The 24-bit RGB interface is widely used in automotive infotainment. In addition to the 24-bit RGB interface, separate slower speed control signals are also needed. The DS90UB925 and DS90UB926 have additional pins for such applications with the additional control signals. Examples of control signals needed to be sent from the H/U (head unit) to display are display enable, display reset, and backlig
Model Line
Series: DS90UH926Q-Q1 (3)
- DS90UH926QSQ/NOPB DS90UH926QSQE/NOPB DS90UH926QSQX/NOPB
Manufacturer's Classification
- Semiconductors > Interface > FPD-Link SerDes > Display SerDes
