Datasheet Texas Instruments DS90UR124

Manufacturer	Texas Instruments
Series	DS90UR124

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Status

Packaging

Parametrics

Parameters / Models	DS90UR124IVS/NOPB	DS90UR124IVSX/NOPB
Color Depth, bpp	18	18
Diagnostics	BIST	BIST
EMI Reduction	Adjustable Progressive Turn On (PTO),Slew Rate Control	Adjustable Progressive Turn On (PTO),Slew Rate Control
Function	Deserializer	Deserializer
Input Compatibility	FPD-Link II LVDS	FPD-Link II LVDS
Operating Temperature Range, C	-40 to 105	-40 to 105
Output Compatibility	LVCMOS	LVCMOS
Package Group	TQFP	TQFP
Package Size: mm2:W x L, PKG	64TQFP: 144 mm2: 12 x 12(TQFP)	64TQFP: 144 mm2: 12 x 12(TQFP)
Pixel Clock Min, MHz	5	5
Pixel Clock(Max), MHz	43	43
Rating	Catalog	Catalog
Signal Conditioning	-	-
Special Features	-	-
Total Throughput, Mbps	1032	1032

Eco Plan

Application Notes

• Download
  AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B)
  PDF, 70 Kb, Revision: B, File published: Apr 26, 2013
  Compliance to EMI limits is often a challenge. Spread spectrum clocking is commonly used to minimize EMI. The effect of modulating periodic signals, both clock and data, reduces the peak emissions by spreading the energy over a range of frequencies. The DS90UR241 and DS90UR124 chipset allows the use of spread spectrum clock and data inputs. The following is a discussion of spread spectrum clock ch
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  AN-1807 FPD-Link II Display SerDes Overview (Rev. B)
  PDF, 45 Kb, Revision: B, File published: Apr 26, 2013
  TI’s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was s
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  LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)
  PDF, 101 Kb, Revision: A, File published: Apr 29, 2013
  This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
• Download
  Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)
  PDF, 118 Kb, Revision: A, File published: Apr 26, 2013
  TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.
• Download
  DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)
  PDF, 170 Kb, Revision: E, File published: Apr 29, 2013
  Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer

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Manufacturer's Classification

• Semiconductors> Interface> Display & Imaging SerDes> FPD-Link II SerDes