Datasheet Texas Instruments SM320C80
Manufacturer | Texas Instruments |
Series | SM320C80 |
Digital Signal Processors
Datasheets
SMJ320C80 Digital Signal Processor datasheet
PDF, 3.4 Mb, Revision: B, File published: Jun 30, 2002
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Status
SM320C80GFM50 | SM320C80HFHM50 | |
---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No |
Packaging
SM320C80GFM50 | SM320C80HFHM50 | |
---|---|---|
N | 1 | 2 |
Pin | 305 | 320 |
Package Type | GF | HFH |
Industry STD Term | CPGA | CFP |
JEDEC Code | S-CPGA-P | R-CQFP-F |
Package QTY | 1 | 1 |
Carrier | JEDEC TRAY (5+1) | |
Device Marking | SM320C80GFM50 | SM320C80HFHM50 |
Width (mm) | 47.25 | 7.63 |
Length (mm) | 47.25 | 7.63 |
Thickness (mm) | 3.3 | 4 |
Pitch (mm) | 1.27 | .5 |
Max Height (mm) | 5.59 | 4.55 |
Mechanical Data | Download | Download |
Parametrics
Parameters / Models | SM320C80GFM50 | SM320C80HFHM50 |
---|---|---|
Cycle Time, ns | 20 | 20 |
DMA, Ch | 1 | 1 |
Data / Program Memory Space, Words | 2.4G | 2.4G |
Frequency, MHz | 50 | 50 |
MIPS | 60 | 60 |
MOPS | 120 | 120 |
Operating Temperature Range, C | -55 to 125 | -55 to 125 |
Package Group | CPGA | CFP |
Pin/Package | 305CPGA, 320CFP | 305CPGA, 320CFP |
Rating | Military | Military |
Eco Plan
SM320C80GFM50 | SM320C80HFHM50 | |
---|---|---|
RoHS | See ti.com | See ti.com |
Application Notes
- Modified Goertzel Algorithm in DTMF Detection Using the TMS320C80 DSPPDF, 101 Kb, File published: Jun 1, 1996
This document presents a modified Goertzel algorithm for DTMF tone detection on a TMS320C80 ('C80) 32-bit multiprocessor digital signal processor (DSP). The algorithm detects the incoming frequency with an offset range plus or minus 1.5%. For this application, a basic implementation is provided, but additional testing is required to make this detection algorithm complete. The appendix provides the - Acoustic Echo Cancellation Algorithms and Implementation on the TMS320C80PDF, 223 Kb, File published: May 1, 1996
Acoustic echo cancellation on the TMS320C8x multiprocessor digital signal processor (DSP) offers high performance and flexibility to meet varying user needs. This document describes the implementation of an integrated N-tap digital acoustic echo canceller on the TMS320C8x parallel processor (PP). A brief discussion of a generic echo cancellation algorithm is provided. A 512-tap (64-ms span) echo - TMS320C8x System-Level Synopsis (Rev. B)PDF, 516 Kb, Revision: B, File published: Sep 1, 1995
The TMS320C8x is Texas Instruments? first generation of single-chipmultiprocessor digital signal processor (DSP) devices. Asingle ?C8x contains up to five powerful, fully programmable pro-cessors:a master processor (MP) and up to four parallel proces-sors(PPs). The MP is a 32-bit RISC (reduced instruction setcomputer) processor with an integral, high-performanceIEEE-754 floating-point
Model Line
Series: SM320C80 (2)
Manufacturer's Classification
- Semiconductors> Processors> Digital Signal Processors> Other High Reliability DSPs