Datasheet Texas Instruments SN54ACT74

Manufacturer	Texas Instruments
Series	SN54ACT74

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Parametrics

Parameters / Models	5962-8752501M2A	5962-8752501MCA	5962-8752501MDA	SNJ54ACT74FK	SNJ54ACT74J	SNJ54ACT74W
3-State Output	No	No	No	No	No	No
Bits	2	2	2	2	2	2
F @ Nom Voltage(Max), Mhz	100	100	100	100	100	100
ICC @ Nom Voltage(Max), mA	0.02	0.02	0.02	0.02	0.02	0.02
Input Type	TTL	TTL	TTL	TTL	TTL	TTL
Operating Temperature Range, C	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125
Output Drive (IOL/IOH)(Max), mA	24/-24	24/-24	24/-24	24/-24	24/-24	24/-24
Output Type	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Package Group	LCCC	CDIP	CFP	LCCC	CDIP	CFP
Package Size: mm2:W x L, PKG	20LCCC: 79 mm2: 8.89 x 8.89(LCCC)	See datasheet (CDIP)	See datasheet (CFP)	20LCCC: 79 mm2: 8.89 x 8.89(LCCC)	See datasheet (CDIP)	See datasheet (CFP)
Rating	Military	Military	Military	Military	Military	Military
Technology Family	ACT	ACT	ACT	ACT	ACT	ACT
VCC(Max), V	5.5	5.5	5.5	5.5	5.5	5.5
VCC(Min), V	4.5	4.5	4.5	4.5	4.5	4.5
tpd @ Nom Voltage(Max), ns	13	13	13	13	13	13

Eco Plan

Application Notes

• Download
  Power-Up Behavior of Clocked Devices (Rev. A)
  PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
• Download
  TI IBIS File Creation Validation and Distribution Processes
  PDF, 380 Kb, File published: Aug 29, 2002
  The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
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  Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
  PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
• Download
  Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
  PDF, 337 Kb, File published: Jul 8, 2004
  Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
• Download
  Selecting the Right Level Translation Solution (Rev. A)
  PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
  Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
• Download
  Designing With Logic (Rev. C)
  PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
  Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
• Download
  Introduction to Logic
  PDF, 93 Kb, File published: Apr 30, 2015
• Download
  Implications of Slow or Floating CMOS Inputs (Rev. D)
  PDF, 260 Kb, Revision: D, File published: Jun 23, 2016
• Download
  CMOS Power Consumption and CPD Calculation (Rev. B)
  PDF, 89 Kb, Revision: B, File published: Jun 1, 1997
  Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
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  Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
  PDF, 43 Kb, File published: Apr 1, 1996
  Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

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Manufacturer's Classification

• Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers