Datasheet Texas Instruments SN54GTL16612

Manufacturer	Texas Instruments
Series	SN54GTL16612

Datasheets

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Parametrics

Parameters / Models	5962-9689001QXA	SNJ54GTL16612WD
Bits	18	18
F @ Nom Voltage(Max), Mhz	95	95
ICC @ Nom Voltage(Max), mA	120	120
Input Type	GTL/GTL+/LVTTL	GTL/GTL+/LVTTL
Operating Temperature Range, C	-55 to 125	-55 to 125
Output Drive (IOL/IOH)(Max), mA	64	64
Output Type	GTL/GTL+/LVTTL	GTL/GTL+/LVTTL
Package Group	CFP	CFP
Package Size: mm2:W x L, PKG	See datasheet (CFP)	See datasheet (CFP)
Rating	Military	Military
Schmitt Trigger	No	No
Technology Family	GTL	GTL
VCC(Max), V	5.25	5.25
VCC(Min), V	3.15	3.15
tpd @ Nom Voltage(Max), ns	6.3	6.3

Eco Plan

Application Notes

• Download
  GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)
  PDF, 184 Kb, Revision: A, File published: Mar 1, 1997
  GTL and BTL transceivers provide high-performance, excellent signal integrity and cost-effectiveness in high-speed backplane and point-to-point applications. This document discusses the GTL and BTL devices input/output (I/O) structure, power consumption, simultaneous switching, slew rate, and signal integrity. Design considerations for using these devices are provided.
• Download
  Understanding Advanced Bus-Interface Products Design Guide
  PDF, 253 Kb, File published: May 1, 1996
• Download
  TI IBIS File Creation Validation and Distribution Processes
  PDF, 380 Kb, File published: Aug 29, 2002
  The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
• Download
  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Kb, File published: May 10, 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
• Download
  Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
  PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
• Download
  Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
  PDF, 337 Kb, File published: Jul 8, 2004
  Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
• Download
  Introduction to Logic
  PDF, 93 Kb, File published: Apr 30, 2015
• Download
  Implications of Slow or Floating CMOS Inputs (Rev. D)
  PDF, 260 Kb, Revision: D, File published: Jun 23, 2016

Model Line

Manufacturer's Classification

• Semiconductors> Space & High Reliability> Logic Products> Backplane Logic (GTL/TTL/BTL/ECL Transceivers/Translators)