Datasheet Texas Instruments SN55LVDS32-SP

SN55LVDS32-SP
www.ti.com SLLSEB4 – MARCH 2012 HIGH-SPEED DIFFERENTIAL LINE RECEIVER
Check for Samples: SN55LVDS32-SP FEATURES 1 QML-V Qualified, SMD 5962-97621
Operate From a Single 3.3-V Supply
Designed for Signaling Rates of up to 100
Mbps
Differential Input Thresholds В±100 mV Max
Typical Propagation Delay Times of 2.1 ns
Power Dissipation 60 mW Typical Per Receiver
at Maximum Data Rate
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
Open-Circuit Fail-Safe
Cold Sparing for Space and High Reliability
Applications Requiring Redundancy J OR W PACKAGE
(TOP VIEW) DESCRIPTION
The SN55LVDS32 is a differential line receiver that implements the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard
levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a
3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a В±100-mV
differential input voltage within the input common-mode voltage range. The input common-mode voltage range
allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver …