Datasheet Texas Instruments SN65LVDS100D
| Manufacturer | Texas Instruments |
| Series | SN65LVDS100 |
| Part Number | SN65LVDS100D |
2 Gbps LVDS/LVPECL/CML to LVDS Buffer/Repeater/Translator 8-SOIC -40 to 85
Datasheets
SN65LVDx10x Differential Translator/Repeater datasheet
PDF, 1.6 Mb, Revision: E, File published: Jul 20, 2015
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 8 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 75 |
| Carrier | TUBE |
| Device Marking | DL100 |
| Width (mm) | 3.91 |
| Length (mm) | 4.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Download |
Parametrics
| Device Type | Buffer |
| ESD HBM | 5 kV |
| Function | Repeater/Translator |
| ICC(Max) | 30 mA |
| Input Signal | CML,LVDS,LVPECL |
| No. of Rx | 1 |
| No. of Tx | 1 |
| Operating Temperature Range | -40 to 85 C |
| Output Signal | LVDS |
| Package Group | SOIC |
| Package Size: mm2:W x L | 8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG |
| Protocols | LVDS |
| Signaling Rate | 2000 Mbps |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: SN65LVDS100EVM
SN65LVDS100 Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: SN65CML100EVM
SN65CML100 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Signaling Rate vs. Distance for Differential BuffersPDF, 420 Kb, File published: Jan 26, 2010
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, File published: Feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revision: C, File published: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Model Line
Series: SN65LVDS100 (8)
Manufacturer's Classification
- Semiconductors > Interface > LVDS/M-LVDS/PECL > Buffers, Drivers/Receivers and Cross-Points
