Datasheet Texas Instruments SN74ABT18646

ManufacturerTexas Instruments
SeriesSN74ABT18646
Datasheet Texas Instruments SN74ABT18646

Scan Test Devices With 18-Bit Bus Transceivers And Registers

Datasheets

Scan Test Devices With 18-Bit Bus Transceivers And Registers datasheet
PDF, 202 Kb, Revision: A, File published: Jan 29, 2002
Extract from the document

Prices

Status

SN74ABT18646PM
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

SN74ABT18646PM
N1
Pin64
Package TypePM
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingABT18646
Width (mm)10
Length (mm)10
Thickness (mm)1.4
Pitch (mm).5
Max Height (mm)1.6
Mechanical DataDownload

Parametrics

Parameters / ModelsSN74ABT18646PM
SN74ABT18646PM
Bits18
F @ Nom Voltage(Max), Mhz150
ICC @ Nom Voltage(Max), mA38
Operating Temperature Range, C-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-32
Package GroupLQFP
Package Size: mm2:W x L, PKG64LQFP: 144 mm2: 12 x 12(LQFP)
RatingCatalog
Technology FamilyABT
VCC(Max), V5.5
VCC(Min), V4.5
Voltage(Nom), V5
tpd @ Nom Voltage(Max), ns6.6

Eco Plan

SN74ABT18646PM
RoHSCompliant

Application Notes

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, File published: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • Quad Flatpack No-Lead Logic Packages (Rev. D)
    PDF, 1.0 Mb, Revision: D, File published: Feb 16, 2004
    Texas Instruments (TI) Quad Flatpack No-lead (QFN) 14/16/20-terminal Pb-free plastic packages meet dimensions specified in JEDEC standard MO-241 allow for board miniaturization and hold several advantages over traditional SOIC SSOP TSSOP and TVSOP packages. The packages are physically smaller have a smaller routing area improved thermal performance and improved electrical parasitics while
  • Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)
    PDF, 528 Kb, Revision: B, File published: Jun 1, 1997
    The purpose of this document is to assist the designers of high-performance digital logic systems in using the advanced BiCMOS technology (ABT) logic family. Detailed electrical characteristics of these bus-interface devices are provided and tables and graphs have been included to compare specific parameters of the ABT family with those of other logic families. In addition typical data is provide
  • Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)
    PDF, 115 Kb, Revision: A, File published: Mar 1, 1997
    Advanced bus-interface logic (ABIL) products processed in submicron advanced BiCMOS technologies (ABT) address the specific end-equipment demands of workstations personal and portable computers and telecommunications markets. This document discusses ABIL as system bus interfaces the merits of ABT its I/O structure packaging and ABT products for end-equipment specific solutions.
  • Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)
    PDF, 80 Kb, Revision: A, File published: Dec 1, 1996
    This document shows the output skew for the ABT16254 ABT16952 and ABT16500A devices of the TI advanced BiCMOS (ABT) family. The data samples show which output skew is being examined where the data originates and how it is analyzed. Some errors present in the data are discussed. Skew curves at varying temperatures are given for the ABT16240 ABT16245 ABT16952 ABT16500A and ABT16249 devic
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, File published: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, File published: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Model Line

Series: SN74ABT18646 (1)

Manufacturer's Classification

  • Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic