Datasheet Texas Instruments SN74ABT8245

ManufacturerTexas Instruments
SeriesSN74ABT8245
Datasheet Texas Instruments SN74ABT8245

Scan Test Devices With Octal Bus Transceivers

Datasheets

Scan Test Devices With Octal Bus Transceivers datasheet
PDF, 810 Kb, Revision: D, File published: Dec 1, 1996
Extract from the document

Prices

Status

SN74ABT8245DWSN74ABT8245DWG4SN74ABT8245DWR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Packaging

SN74ABT8245DWSN74ABT8245DWG4SN74ABT8245DWR
N123
Pin242424
Package TypeDWDWDW
Industry STD TermSOICSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY25252000
CarrierTUBETUBELARGE T&R
Device MarkingABT8245ABT8245ABT8245
Width (mm)7.57.57.5
Length (mm)15.415.415.4
Thickness (mm)2.352.352.35
Pitch (mm)1.271.271.27
Max Height (mm)2.652.652.65
Mechanical DataDownloadDownloadDownload

Parametrics

Parameters / ModelsSN74ABT8245DW
SN74ABT8245DW
SN74ABT8245DWG4
SN74ABT8245DWG4
SN74ABT8245DWR
SN74ABT8245DWR
Bits888
F @ Nom Voltage(Max), Mhz150150150
ICC @ Nom Voltage(Max), mA383838
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-3264/-32
Package GroupSOICSOICSOIC
Package Size: mm2:W x L, PKG24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)
RatingCatalogCatalogCatalog
Technology FamilyABTABTABT
VCC(Max), V5.55.55.5
VCC(Min), V4.54.54.5
Voltage(Nom), V555
tpd @ Nom Voltage(Max), ns5.85.85.8

Eco Plan

SN74ABT8245DWSN74ABT8245DWG4SN74ABT8245DWR
RoHSCompliantCompliantCompliant

Application Notes

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, File published: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • Quad Flatpack No-Lead Logic Packages (Rev. D)
    PDF, 1.0 Mb, Revision: D, File published: Feb 16, 2004
    Texas Instruments (TI) Quad Flatpack No-lead (QFN) 14/16/20-terminal Pb-free plastic packages meet dimensions specified in JEDEC standard MO-241 allow for board miniaturization and hold several advantages over traditional SOIC SSOP TSSOP and TVSOP packages. The packages are physically smaller have a smaller routing area improved thermal performance and improved electrical parasitics while
  • Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)
    PDF, 528 Kb, Revision: B, File published: Jun 1, 1997
    The purpose of this document is to assist the designers of high-performance digital logic systems in using the advanced BiCMOS technology (ABT) logic family. Detailed electrical characteristics of these bus-interface devices are provided and tables and graphs have been included to compare specific parameters of the ABT family with those of other logic families. In addition typical data is provide
  • Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)
    PDF, 115 Kb, Revision: A, File published: Mar 1, 1997
    Advanced bus-interface logic (ABIL) products processed in submicron advanced BiCMOS technologies (ABT) address the specific end-equipment demands of workstations personal and portable computers and telecommunications markets. This document discusses ABIL as system bus interfaces the merits of ABT its I/O structure packaging and ABT products for end-equipment specific solutions.
  • Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)
    PDF, 80 Kb, Revision: A, File published: Dec 1, 1996
    This document shows the output skew for the ABT16254 ABT16952 and ABT16500A devices of the TI advanced BiCMOS (ABT) family. The data samples show which output skew is being examined where the data originates and how it is analyzed. Some errors present in the data are discussed. Skew curves at varying temperatures are given for the ABT16240 ABT16245 ABT16952 ABT16500A and ABT16249 devic
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, File published: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, File published: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic