Datasheet Texas Instruments SN74ACT3632-15PQG4
| Manufacturer | Texas Instruments |
| Series | SN74ACT3632 |
| Part Number | SN74ACT3632-15PQG4 |
512 x 36 x 2 bidirectional synchronous FIFO memory 132-BQFP 0 to 70
Datasheets
512 X 36 X 2 Clocked Bidirectional First-In, First-Out Memory datasheet
PDF, 497 Kb, Revision: D, File published: Apr 1, 1998
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 132 |
| Package Type | PQ |
| Industry STD Term | BQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 36 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | ACT3632-15 |
| Width (mm) | 24.13 |
| Length (mm) | 27.44 |
| Thickness (mm) | 3.56 |
| Pitch (mm) | .635 |
| Max Height (mm) | 4.57 |
| Mechanical Data | Download |
Parametrics
| Package Group | BQFP |
| Package Size: mm2:W x L | 132BQFP: 768 mm2: 27.495 x 27.945(BQFP) PKG |
| Schmitt Trigger | No |
Eco Plan
| RoHS | Compliant |
Application Notes
- Interfacing TI Clocked FIFOs With TI Floating-Point DSPs (Rev. A)PDF, 108 Kb, Revision: A, File published: Mar 1, 1996
FIFO memories are used in digital signal processing systems for matching data paths with asynchronous clock or data rates. This document shows the SN74ACT3632 512?36?2 clocked FIFO as a single-chip bi-directional buffering solution that interfaces to the TI TMS320C3x and TMS320C4x floating-point DSP family. Programmable FIFO flags enable DMA control techniques that are used to handle the data flow - Power-Dissipation Calculations for TI FIFO Products (Rev. A)PDF, 106 Kb, Revision: A, File published: Mar 1, 1996
Low power consumption is a major advantage of TI FIFO products. Power calculations are required to meet design requirements for chip temperature and system power. This document assists component and system designers in evaluating power consumption for the ACT and ABT FIFO products. Two examples of power calculations, one for the SN74ACT3632 bi-directional CMOS FIFO and one for the BiCMOS SN74ABT36 - FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (Rev. A)PDF, 65 Kb, Revision: A, File published: Mar 1, 1996
The TI 32- and 36-bit FIFOs contain mailbox-bypass registers that transmit priority from one FIFO port to the other, port A to B or port B to A with out storing the data in the FIFO SRAM buffer. This document describes the FIFO mailbox-bypass registers and shows an example of direct memory access (DMA) control of a digital signal processor (DSP). The components described are the SN74ACT3641 and th - Simultaneous-Switching Noise Analysis For Texas Instruments FIFO Products (Rev. A)PDF, 147 Kb, Revision: A, File published: Mar 1, 1996
In the high-speed advanced logic families, including ACT and ABT FIFO products, analysis of circuit noise immunity during simultaneous switching of multiple outputs is crucial. This document provides a thorough explanation of noise reduction techniques for TI FIFO devices. It is designed to assist component and system design engineers in the evaluation of simultaneous switching noise for ACT and A
Model Line
Series: SN74ACT3632 (3)
- SN74ACT3632-15PCB SN74ACT3632-15PQ SN74ACT3632-15PQG4
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > FIFO Register
Other Names:
SN74ACT363215PQG4, SN74ACT3632 15PQG4
